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cannot be written to\n- 32 bit Program Counter (PC)  \n- No flag registers (carry, zero, sign..etc)  \n- Few Addresing Modes  \n- Only Load and Store instructions can access memory  \n- We assume memory word size is 32 bits (word addressable)\n  \n## ▫️ Addressing Modes  \n| Addressing Mode | Example Instruction |\n| -------------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- |\n| Register addressing | ADD R1,R2,R3      |\n| Immediate addressing | ADDI R1,R2, 200       |\n| Base addressing      | LW R5, 150(R7)    |\n| PC relative addressing  | BEQZ R3, Label   |\n| Pseudo-direct addressing | J Label      |\n\n\n## ▫️ Instructions Considered  \nNot all instructions of MIPS32 are considered in this design, for implementation sake only a few instructions are considered, mentioned below:  \n- Load and Store Instructions  \n```\nLW R2,124(R8) // R2 = Mem[R8+124]  \nSW R5,-10(R25) // Mem[R25-10] = R5  \n```\n- Arithmetic and Logic Instructions (only register operands)  \n```\nADD R1,R2,R3 // R1 = R2 + R3  \nADD R1,R2,R0 // R1 = R2 + 0  \nSUB R12,R10,R8 // R12 = R10 – R8  \nAND R20,R1,R5 // R20 = R1 \u0026 R5  \nOR R11,R5,R6 // R11 = R5 | R6  \nMUL R5,R6,R7 // R5 = R6 * R7  \nSLT R5,R11,R12 // If R11 \u003c R12, R5=1; else R5=0 \n```\n- Arithmetic and Logic Instructions (immediate operand)  \n```\nADDI R1,R2,25 // R1 = R2 + 25  \nSUBI R5,R1,150 // R5 = R1 – 150  \nSLTI R2,R10,10 // If R10\u003c10, R2=1; else R2=0 \n```\n- Branch Instructions  \n```\nBEQZ R1,Loop // Branch to Loop if R1=0  \nBNEQZ R5,Label // Branch to Label if R5!=0  \n```\n- Jump Instruction  \n```\nJ Loop // Branch to Loop unconditionally  \n```\n- Miscellaneous Instructioon  \n```\nHLT // Halt execution \n```\n\n## ▫️ Instruction Encoding  \n![ISR](https://user-images.githubusercontent.com/68592620/231771092-0c93aeb3-6b01-478f-a363-ecadb1ec578a.png)  \n- shamt : shift amount, funct : opcode extension for additional functions.\n- Some instructions require two register operands rs \u0026 rt as input, while some require only rs. \n- This requirement is only identified only after the instruction is decoded. \n- While decoding is going on, we can prefetch the registers in parallel, which may or may not be used later. \n- Similarly, the 16-bit and 26-bit immediate data are retrieved and signextended to 32-bits in case they are required later.\n  \n## ▫️ Stages of Execution  \nThe instruction execution cycle contains the following 5 stages in order:  \n1. IF : Instruction Fetch  \n2. ID : Instruction Decode / Register Fetch  \n3. EX : Execution / Effective Address Calculation  \n4. MEM : Memory Access / Branch Completion  \n5. WB : Register Write-back  \n- micro operations not shown here.\n  \n## ▫️ Non Pipelined DataPath  \n![nonpipelined](https://user-images.githubusercontent.com/68592620/231771101-f7ea7e00-5c8c-4b6d-ae0c-a0419066e7ad.png)  \n\n## ▫️ Pipelined DataPath  \n![pipelined](https://user-images.githubusercontent.com/68592620/231771102-12c05fa9-6e74-4835-abc6-1bd9b20e8453.png)  \n\n## ▫️ Example Test 1   \n \nInstructions :  \n| Assembly Instruction  | Machine Code | Hexcode |  \n| ------------- | ------------- | ------------- |  \n| ADDI R1,R0,10  | 001010 00000 00001 0000000000001010  | 2801000a  |  \n| ADDI R2,R0,20 | 001010 00000 00010 0000000000010100  | 28020014  |  \n| ADDI R3,R0,25 | 001010 00000 00011 0000000000011001  | 28030019  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| ADD R4,R1,R2 | 000000 00001 00010 00100 00000 000000  | 00222000  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800 |  \n| ADD R5,R4,R3 | 000000 00100 00011 00101 00000 000000  | 00832800  |  \n| HLT | 111111 00000 00000 00000 00000 000000  | fc000000  |  \n\n\nWaveform :  \n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/test1%20(2).png)\n\nConsole output :  \n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/test1%20(1).png)\n\n## ▫️ Example Test 2\n\nInstructions :  \n| Assembly Instruction  | Machine Code | Hexcode |  \n| ------------- | ------------- | ------------- |  \n| ADDI R1,R0,10  | 001010 00000 00001 0000000000001010  | 2801000a  |  \n| ADDI R2,R0,20 | 001010 00000 00010 0000000000010100  | 28020014  |  \n| ADDI R3,R0,25 | 001010 00000 00011 0000000000011001  | 28030019  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| ADD R4,R1,R2 | 000000 00001 00010 00100 00000 000000  | 00222000  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800 |  \n| ADD R5,R4,R3 | 000000 00100 00011 00101 00000 000000  | 00832800  |  \n| HLT | 111111 00000 00000 00000 00000 000000  | fc000000  |  \n\nWaveform:\n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/Screenshot%202025-08-30%20160054.png)\n\nConsole Output:\n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/test2.png)\n\n\n## ▫️ Example Test 3\n\nInstructions :  \n| Assembly Instruction  | Machine Code | Hexcode |  \n| ------------- | ------------- | ------------- |  \n| ADDI R1,R0,10  | 001010 00000 00001 0000000000001010  | 2801000a  |  \n| ADDI R2,R0,20 | 001010 00000 00010 0000000000010100  | 28020014  |  \n| ADDI R3,R0,25 | 001010 00000 00011 0000000000011001  | 28030019  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800  |  \n| ADD R4,R1,R2 | 000000 00001 00010 00100 00000 000000  | 00222000  |  \n| OR R7,R7,R7 (dummy)| 001010 00000 00011 0000000000011001  | 0ce77800 |  \n| ADD R5,R4,R3 | 000000 00100 00011 00101 00000 000000  | 00832800  |  \n| HLT | 111111 00000 00000 00000 00000 000000  | fc000000  |  \n\nWaveform:\n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/test3.png)\n\nConsole Output:\n\n![](https://github.com/SUHANI102003/32-bit-Pipelined-MIPS-Processor/blob/main/sim_logs/test3%20(2).png)\n\n\n## ▫️ Known problems and issues  \nFollowing pipelining hazards are present in the given design :  \n- Structural Hazards due to shared hardware.  \n- Data Hazards due to instruction data dependency.  \n- Control hazards due to branch instructions.  \n## ▫️ References  \n[NPTEL \\\u0026 IIT KGP 'Hardware Modeling using Verilog'- Prof. Indranil Sengupta](https://nptel.ac.in/courses/106105165)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsuhani102003%2F32-bit-pipelined-mips-processor","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsuhani102003%2F32-bit-pipelined-mips-processor","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsuhani102003%2F32-bit-pipelined-mips-processor/lists"}