{"id":23562159,"url":"https://github.com/suyashmahar/urisc","last_synced_at":"2026-01-24T23:32:11.042Z","repository":{"id":54215395,"uuid":"122578220","full_name":"suyashmahar/urisc","owner":"suyashmahar","description":"Single instruction processor and toolchain","archived":false,"fork":false,"pushed_at":"2019-08-14T19:56:13.000Z","size":93,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-10-11T21:48:38.407Z","etag":null,"topics":["fpga","processor-architecture","systemverilog","urisc"],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/suyashmahar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-02-23T05:39:21.000Z","updated_at":"2025-07-01T06:02:51.000Z","dependencies_parsed_at":"2022-08-13T09:20:49.258Z","dependency_job_id":null,"html_url":"https://github.com/suyashmahar/urisc","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/suyashmahar/urisc","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/suyashmahar%2Furisc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/suyashmahar%2Furisc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/suyashmahar%2Furisc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/suyashmahar%2Furisc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/suyashmahar","download_url":"https://codeload.github.com/suyashmahar/urisc/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/suyashmahar%2Furisc/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28738997,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-24T22:12:27.248Z","status":"ssl_error","status_checked_at":"2026-01-24T22:12:10.529Z","response_time":89,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","processor-architecture","systemverilog","urisc"],"created_at":"2024-12-26T16:15:35.533Z","updated_at":"2026-01-24T23:32:11.001Z","avatar_url":"https://github.com/suyashmahar.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"![build-status](https://travis-ci.com/suyashmahar/urisc.svg?token=JoPidbExBPkazChjCZLp\u0026branch=master)  \nUltra Reduced Instruction Set Computer (URISC)\n====\n\nUltra Reduced Instruction Set Computers use extremely limited set of instructions, in this case just a single instruction, `subleq`.   More details on this is available in [docs/architecture/architecture.md](architecture/architecture.md)\n\nOverview\n----\n\nThis project contains:  \n#### Hardware  \n1. **[URISC core](src/urisc.sv)**. Implements the essential cpu stuff to execute instructions when supplied. URISC uses three clock cycles to execute an instruction (pos-edge).  \n2. **[IO arbiter](src/ioArbiter.sv)**. Arbitrates the memory among the IO devices. Allows the VGA controller to read from the memory and the PS2 controller to write to the memory. Memory access is granted on a round-robin manner to all the registered IO devices (synthesis-time).\n3. **VGA controller**. Standard VGA controller stuff, sync generator, frame buffer... . Currently non-functional 😢.  \n4. **PS2 controller**. Standard PS2 controller to read the key-codes, convert them to ASCII and write to the key buffer.\n\n#### Toolchain  \n1. **Assembler**. The assembler is a [collection of python scripts](toolchain/python-based) that can take a program written in a custom assembly language and converts it to memory coefficient file (\\*.coe) for the processor.  \nThe assembler provides complete support for recursive macro substitution, constant declaration, labels and importing other *.asm files.  \n*Note: An experimental and incomplete [Haskell based assembler](toolchain/assembler.hs) also dwells in the toolchain directory.*  \n2. **Tests and Examples**. The examples are limited at this stage, an attempt to implement the MIPS ISA with limited instruction support is available [here](tests/toolchain/mips.asm). This can be used to compile the infinite loop example available [here](tests/toolchain/sample.asm).  \n\n \nExecution\n----\nHere is a (potato quality) video showing the execution of URISC core, the 8 LEDs from the right shows the PC in base 2.  \n\u003cimg src=\"https://i.imgur.com/4b6M29h.jpg\"/\u003e\n\n\nContributor\n----\n\n[Suyash Mahar](https://suyashmahar.github.io)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsuyashmahar%2Furisc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsuyashmahar%2Furisc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsuyashmahar%2Furisc/lists"}