{"id":16117577,"url":"https://github.com/t-k-233/risc-v-single-cycle-cpu","last_synced_at":"2026-01-27T23:47:15.451Z","repository":{"id":43664615,"uuid":"256442455","full_name":"T-K-233/RISC-V-Single-Cycle-CPU","owner":"T-K-233","description":"RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel","archived":false,"fork":false,"pushed_at":"2025-02-06T07:39:05.000Z","size":17555,"stargazers_count":429,"open_issues_count":1,"forks_count":45,"subscribers_count":10,"default_branch":"main","last_synced_at":"2025-02-06T08:34:27.061Z","etag":null,"topics":["chisel","logisim","risc-v","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/T-K-233.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-04-17T08:12:36.000Z","updated_at":"2025-02-06T07:39:09.000Z","dependencies_parsed_at":"2024-07-24T06:15:39.380Z","dependency_job_id":null,"html_url":"https://github.com/T-K-233/RISC-V-Single-Cycle-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/T-K-233%2FRISC-V-Single-Cycle-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/T-K-233%2FRISC-V-Single-Cycle-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/T-K-233%2FRISC-V-Single-Cycle-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/T-K-233%2FRISC-V-Single-Cycle-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/T-K-233","download_url":"https://codeload.github.com/T-K-233/RISC-V-Single-Cycle-CPU/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247459587,"owners_count":20942248,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","logisim","risc-v","verilog"],"created_at":"2024-10-09T20:45:37.359Z","updated_at":"2026-01-27T23:47:10.433Z","avatar_url":"https://github.com/T-K-233.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V Single Cycle CPU\n\n![Cover Image](docs/cover.jpg)\n\n---\n\n![Result Image](docs/result.jpg)\n\n\n## Notes\n\n- Single page version can achieve ~300 Hz clock rate on a i7-6700K computer.\n\n## Terms and Conditions\n\nThe software [Logisim-evoluion](https://github.com/logisim-evolution/logisim-evolution) is released under the terms of the [GNU GENERAL PUBLIC LICENSE (GPL)](https://github.com/logisim-evolution/logisim-evolution/blob/master/LICENSE.md). For your convenience, the jar file is included in this repository in accordance with the redistribution guideline of the GPL-3.0 license agreement.\n\nThis project is under MIT License. \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ft-k-233%2Frisc-v-single-cycle-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ft-k-233%2Frisc-v-single-cycle-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ft-k-233%2Frisc-v-single-cycle-cpu/lists"}