{"id":29821902,"url":"https://github.com/tahirzia-1/fpga-morse-code-encoder","last_synced_at":"2026-02-06T22:32:53.390Z","repository":{"id":306751764,"uuid":"1027103286","full_name":"TahirZia-1/FPGA-Morse-Code-Encoder","owner":"TahirZia-1","description":"Converts digits (only) into its Morse code on a NEXYS 4 DDR Board, displayed using LED lights. 1 second for dot and 3 seconds for Dash. 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The system supports two operational modes: **Single-Digit Mode** for encoding one digit at a time and **Number Mode** for storing and encoding up to six digits using a FIFO buffer. The design leverages Verilog HDL, a finite state machine (FSM), and a debouncer to ensure reliable operation. This README provides a comprehensive guide to the project's functionality, setup, and usage.\n\n## Features\n- **Two Operating Modes**:\n  - **Single-Digit Mode**: Converts a single digit (set via switches SW0-SW3) into its Morse code equivalent when BTN1 is pressed.\n  - **Number Mode**: Stores up to six digits in a FIFO buffer (using SW0-SW3 and BTN1) and encodes them sequentially when BTN2 is pressed.\n- **Inputs**:\n  - 100 MHz clock (clk)\n  - Reset button (BTN0)\n  - Start/Store button (BTN1)\n  - Encode Number button (BTN2)\n  - 5-bit switches (SW4 for mode selection, SW0-SW3 for digit input)\n- **Outputs**:\n  - LED (LD0): Displays Morse code (dot: 1s ON, dash: 3s ON, element space: 0.5s OFF, inter-digit gap: 2s OFF)\n  - State LED (LD1): Indicates active encoding state\n- **Timing**:\n  - Dot: 1 second\n  - Dash: 3 seconds\n  - Space between elements: 0.5 seconds\n  - Inter-digit gap: 2 seconds\n- **Debouncing**: Ensures reliable button inputs using a 10ms debounce circuit at 100 MHz.\n- **FIFO Buffer**: Stores up to six digits in Number Mode for sequential encoding.\n\n## Project Structure\n- **Morse.sv**: Contains the Verilog modules:\n  - `debouncer`: Debounces button inputs to eliminate noise.\n  - `morse_encoder`: Core FSM and logic for Morse code encoding, including FIFO management.\n  - `morse_top`: Top-level module integrating debouncers and encoder.\n- **Morse_xdc.xdc**: Constraints file mapping inputs (SW0-SW4, BTN0-BTN2) and outputs (LD0, LD1) to Nexys 4 DDR board pins.\n- **Report.pdf**: Detailed design report, including hardware implementation, testing phases, and conclusions.\n\n## Morse Code Patterns\nThe system encodes digits 0-9 into Morse code as follows (dots and dashes are represented as 1s and 0s in a 5-bit pattern):\n\n| Digit | Morse Pattern | Verilog Pattern (5-bit) |\n|-------|---------------|------------------------|\n| 0     | -----         | 00000                  |\n| 1     | .----         | 10000                  |\n| 2     | ..---         | 11000                  |\n| 3     | ...--         | 11100                  |\n| 4     | ....-         | 11110                  |\n| 5     | .....         | 11111                  |\n| 6     | -....         | 01111                  |\n| 7     | --...         | 00111                  |\n| 8     | ---..         | 00011                  |\n| 9     | ----.         | 00001                  |\n\n## Hardware Requirements\n- **FPGA Board**: Nexys 4 DDR (or compatible Nexys A7 board)\n- **Software**: Xilinx Vivado Design Suite for synthesis and implementation\n- **Inputs**:\n  - Switches: SW0-SW3 for digit input, SW4 for mode selection (0: Single-Digit Mode, 1: Number Mode)\n  - Buttons: BTN0 (reset), BTN1 (start/store), BTN2 (encode number)\n- **Outputs**:\n  - LD0: Morse code output\n  - LD1: Encoding state indicator\n\n## Setup and Installation\n1. **Clone the Repository**:\n   ```bash\n   git clone \u003crepository_url\u003e\n   ```\n2. **Open Vivado**:\n   - Launch Xilinx Vivado and create a new project targeting the Nexys 4 DDR board (XC7A100T-1CSG324C).\n3. **Add Source Files**:\n   - Add `Morse.sv` as the design source.\n   - Add `Morse_xdc.xdc` as the constraints file.\n4. **Synthesis and Implementation**:\n   - Run synthesis, implementation, and generate the bitstream in Vivado.\n   - Program the Nexys 4 DDR board with the generated bitstream.\n5. **Verify Pin Assignments**:\n   - Ensure the pin mappings in `Morse_xdc.xdc` match the Nexys 4 DDR board specifications:\n     - Clock: E3\n     - Switches: J15 (SW0), L16 (SW1), M13 (SW2), R15 (SW3), R17 (SW4)\n     - Buttons: M17 (BTN0), P17 (BTN1), M18 (BTN2)\n     - LEDs: H17 (LD0), V11 (LD1)\n\n## Usage\n### Single-Digit Mode (SW4 = 0)\n1. Set SW4 to 0 to select Single-Digit Mode.\n2. Configure SW0-SW3 to represent a digit (0-9) in binary (e.g., 0010 for 2).\n3. Press BTN1 to start encoding.\n4. Observe the Morse code output on LD0 (e.g., for digit 2, see `..---`).\n5. LD1 lights up during encoding.\n6. Press BTN0 to reset the system.\n\n### Number Mode (SW4 = 1)\n1. Set SW4 to 1 to select Number Mode.\n2. Configure SW0-SW3 to a digit (0-9) and press BTN1 to store (up to 6 digits).\n3. Repeat step 2 for additional digits.\n4. Press BTN2 to encode all stored digits sequentially.\n5. Observe the Morse code output on LD0 with a 2-second gap between digits.\n6. LD1 lights up during encoding.\n7. Press BTN0 to reset the system.\n\n### Example Test Cases\n- **Single-Digit Mode**:\n  - Set SW0-SW3 to 0010 (digit 2), SW4 to 0, press BTN1: LD0 displays `..---` (2s ON, 0.5s OFF, 2s ON, 0.5s OFF, 1s ON, 0.5s OFF, 1s ON, 0.5s OFF, 1s ON).\n- **Number Mode**:\n  - Set SW4 to 1, enter digits 3 (0011) and 5 (0101) with BTN1, then press BTN2: LD0 displays `...--` (for 3), 2s gap, then `.....` (for 5).\n\n## Design Details\n- **Debouncer**: Eliminates button bounce with a 10ms delay (1,000,000 cycles at 100 MHz).\n- **FSM States**:\n  - IDLE: Waiting for input, LED off.\n  - ENCODING_DIGIT: Outputs Morse code for the current digit.\n  - INTER_DIGIT_GAP: Inserts a 2-second gap between digits in Number Mode.\n- **FIFO Buffer**: Stores up to six 4-bit digits in Number Mode, managed by write and read pointers.\n- **Timing**: Precise timing for dots, dashes, spaces, and gaps is achieved using a 100 MHz clock and cycle counts.\n\n## Testing and Validation\n- **Phase 1**: Verified Single-Digit Mode by encoding digit 2 (SW0-SW3 = 0010), confirming `..---` on LD0 and LD1 indicating active encoding.\n- **Phase 2**: Verified Number Mode by storing digits 3 (0011) and 5 (0101), then encoding with BTN2, confirming `...--` followed by a 2s gap and `.....` on LD0.\n- **Simulation**: Waveforms validated FSM transitions and timing.\n- **Synthesis Metrics**: Efficient resource usage confirmed via Vivado reports.\n\n## Challenges and Solutions\n- **Button Bounce**: Addressed by implementing a debouncer module.\n- **FIFO Management**: Optimized write and read pointers to prevent overflow and ensure correct digit sequencing.\n- **Timing Accuracy**: Calibrated cycle counts for precise Morse code timing at 100 MHz.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftahirzia-1%2Ffpga-morse-code-encoder","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftahirzia-1%2Ffpga-morse-code-encoder","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftahirzia-1%2Ffpga-morse-code-encoder/lists"}