{"id":13599894,"url":"https://github.com/takahirox/riscv-rust","last_synced_at":"2025-11-13T22:58:02.014Z","repository":{"id":39776989,"uuid":"235231816","full_name":"takahirox/riscv-rust","owner":"takahirox","description":"RISC-V processor emulator written in Rust+WASM","archived":false,"fork":false,"pushed_at":"2023-04-06T19:27:22.000Z","size":37346,"stargazers_count":657,"open_issues_count":45,"forks_count":51,"subscribers_count":24,"default_branch":"master","last_synced_at":"2025-05-12T06:15:34.367Z","etag":null,"topics":["cpu","emulator","processor","risc-v","riscv","rust","wasm","webassembly"],"latest_commit_sha":null,"homepage":"https://takahirox.github.io/riscv-rust/wasm/web/index.html","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/takahirox.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2020-01-21T01:28:18.000Z","updated_at":"2025-05-10T13:35:19.000Z","dependencies_parsed_at":"2024-02-06T04:51:16.998Z","dependency_job_id":null,"html_url":"https://github.com/takahirox/riscv-rust","commit_stats":{"total_commits":381,"total_committers":4,"mean_commits":95.25,"dds":0.007874015748031482,"last_synced_commit":"8ee69d7a5dc7ef6d8b2bda96bf86d2923f2cf176"},"previous_names":[],"tags_count":3,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/takahirox%2Friscv-rust","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/takahirox%2Friscv-rust/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/takahirox%2Friscv-rust/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/takahirox%2Friscv-rust/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/takahirox","download_url":"https://codeload.github.com/takahirox/riscv-rust/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253685240,"owners_count":21947309,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","emulator","processor","risc-v","riscv","rust","wasm","webassembly"],"created_at":"2024-08-01T17:01:16.415Z","updated_at":"2025-11-13T22:58:01.971Z","avatar_url":"https://github.com/takahirox.png","language":"Rust","funding_links":[],"categories":["Rust","Tools"],"sub_categories":["Mesh networks"],"readme":"# riscv-rust\n\n[![Build Status](https://travis-ci.org/takahirox/riscv-rust.svg?branch=master)](https://travis-ci.org/takahirox/riscv-rust)\n[![Crate](https://img.shields.io/crates/v/riscv_emu_rust.svg)](https://crates.io/crates/riscv_emu_rust)\n[![npm version](https://badge.fury.io/js/riscv_emu_rust_wasm.svg)](https://badge.fury.io/js/riscv_emu_rust_wasm)\n\nriscv-rust is a [RISC-V](https://riscv.org/) processor and peripheral devices emulator project written in Rust and compiled to WebAssembly. You can import RISC-V emulator into your Rust or JavaScript project. Refer to the [Slides](https://docs.google.com/presentation/d/1qeR6KMSaJTR0ZSa2kLxgcBuc_zBo3l-kYbOpq1Wqmi0/edit?usp=sharing) for more detail.\n\n## Online Demo\n\nYou can run Linux or xv6 on the emulator in your browser. [Online demo is here](https://takahirox.github.io/riscv-rust/wasm/web/index.html)\n\n## Screenshots\n\n![animation](./screenshots/animation.gif)\n![debugger](./screenshots/debugger.gif)\n\n## Documents\n\n* [Document](https://docs.rs/riscv_emu_rust/0.2.0/riscv_emu_rust/)\n\n## Features\n\n- Emulate RISC-V processor and peripheral devices\n- Stable as [Linux](https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html) and [xv6-riscv](https://github.com/mit-pdos/xv6-riscv) run on it\n- Linux OpenSBI and legacy BBL boot support\n- Runnable locally\n- Also runnable in browser with WebAssembly\n- Debugger\n- You can import RISC-V emulator into your Rust or JavaScript project\n\n## Instructions/Features support status\n\n- [x] RV32/64I\n- [x] RV32/64M\n- [x] RV32/64F (almost)\n- [x] RV32/64D (almost)\n- [ ] RV32/64Q\n- [x] RV32/64A (almost)\n- [x] RV64C/32C (almost)\n- [x] RV32/64Zifencei (almost)\n- [x] RV32/64Zicsr (almost)\n- [x] CSR (almost)\n- [x] SV32/39\n- [ ] SV48\n- [x] Privileged instructions (almost)\n- [ ] PMP\n\netc...\n\nThe emulator supports almost all instructions listed above but some instructions which are not used in Linux or xv6 are not implemented yet. Your contribution is very welcome.\n\n## How to import into your Rust project\n\nThe emulator module is released at [crates.io](https://crates.io/crates/riscv_emu_rust\n). Add the following line into Cargo.toml of your Rust project.\n\n```\n[dependencies]\nriscv_emu_rust = \"0.2.0\"\n```\n\nRefer to [Document](https://docs.rs/riscv_emu_rust/0.2.0/riscv_emu_rust/struct.Emulator.html) for the API.\n\n## How to build core library locally\n\n```sh\n$ git clone https://github.com/takahirox/riscv-rust.git\n$ cd riscv-rust\n$ cargo build --release\n```\n\n## How to run Linux or xv6 as desktop application\n\n```sh\n$ cd riscv-rust/cli\n# Run Linux\n$ cargo run --release ../resources/linux/opensbi/fw_payload.elf -f ../resources/linux/rootfs.img\n# Run xv6\n$ cargo run --release ../resources/xv6/kernel -f ../resources/xv6/fs.img\n```\n\n## How to run riscv-tests\n\nPrerequirements\n- Install [riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain)\n- Install [riscv-tests](https://github.com/riscv/riscv-tests)\n\n```sh\n$ cd riscv-rust/cli\n$ cargo run $path_to_riscv_tets/isa/rv32ui-p-add -n\n```\n\n## How to import and use WebAssembly RISC-V emulator in a web browser\n\nSee [wasm/web](https://github.com/takahirox/riscv-rust/tree/master/wasm/web)\n\n## How to install and use WebAssembly RISC-V emulator npm package\n\nSee [wasm/npm](https://github.com/takahirox/riscv-rust/tree/master/wasm/npm)\n\n## Links\n\n### Linux RISC-V port\n\n[Running 64- and 32-bit RISC-V Linux on QEMU](https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html)\n\n### xv6-riscv\n\n[xv6-riscv](https://github.com/mit-pdos/xv6-riscv) is the RISC-V port of [xv6](https://pdos.csail.mit.edu/6.828/2019/xv6.html) which is UNIX V6 rewritten by MIT for x86 in the current C language.\n\n### Specifications\n\n- [RISC-V ISA](https://riscv.org/specifications/)\n- [Virtio Device](https://docs.oasis-open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.html)\n- [UART](http://www.ti.com/lit/ug/sprugp1/sprugp1.pdf)\n- [CLINT, PLIC (SiFive E31 Manual)](https://sifive.cdn.prismic.io/sifive%2Fc89f6e5a-cf9e-44c3-a3db-04420702dcc1_sifive+e31+manual+v19.08.pdf)\n- [SiFive Interrupt Cookbook](https://sifive.cdn.prismic.io/sifive/0d163928-2128-42be-a75a-464df65e04e0_sifive-interrupt-cookbook.pdf)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftakahirox%2Friscv-rust","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftakahirox%2Friscv-rust","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftakahirox%2Friscv-rust/lists"}