{"id":15060260,"url":"https://github.com/tasmirz/computer","last_synced_at":"2026-01-02T08:05:41.645Z","repository":{"id":229040910,"uuid":"775605579","full_name":"tasmirz/Computer","owner":"tasmirz","description":"A 29bit , 5 Stage pipelined RISC computer with dedicated assembler.","archived":false,"fork":false,"pushed_at":"2025-02-27T14:52:50.000Z","size":3363,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-15T05:14:45.500Z","etag":null,"topics":["assembler","logisim-computer","logisim-cpu","logisim-evolution","risc"],"latest_commit_sha":null,"homepage":"","language":"Jupyter Notebook","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"agpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/tasmirz.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-03-21T17:41:45.000Z","updated_at":"2025-02-27T14:52:54.000Z","dependencies_parsed_at":"2024-03-21T18:55:01.059Z","dependency_job_id":"899517ea-94ef-41af-ad97-7d598881e9ef","html_url":"https://github.com/tasmirz/Computer","commit_stats":null,"previous_names":["tasmirz/computer"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tasmirz%2FComputer","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tasmirz%2FComputer/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tasmirz%2FComputer/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tasmirz%2FComputer/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/tasmirz","download_url":"https://codeload.github.com/tasmirz/Computer/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243685583,"owners_count":20330982,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","logisim-computer","logisim-cpu","logisim-evolution","risc"],"created_at":"2024-09-24T22:55:16.712Z","updated_at":"2026-01-02T08:05:41.633Z","avatar_url":"https://github.com/tasmirz.png","language":"Jupyter Notebook","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Computer emulation in Logisim Evolution\n\n\u003cfigure\u003e\n\u003cimg src=\"./assets/output.gif\"\u003e\n\u003ccaption\u003e An early stage program showcasing Output\u003c/caption\u003e\n\u003c/figure\u003e\n\u003cbr\u003e\n\u003cbr\u003e\n\u003cfigure\u003e\n\u003cimg src=\"./assets/io.gif\"\u003e\n\u003ccaption\u003e I/O Operation\u003c/caption\u003e\n\u003c/figure\u003e\n\u003cbr\u003e\n\u003cbr\u003e\n\u003cbr\u003e\nHello There!\nIt's a repository showcasing my CSE2114 (Computer Architecture Sessional) project. The task was to build a 29 bit computer with at least 4 instructions. As it was an open ended project I added some extra objectives.\n\n## Objectives\n\n- [x] Building a computer with instruction set similar to **RISC-V** , in **Harvard architecture**\n- [x] Make the computer five stage **pipelined**\n- [x] The computer should support **IO** device interfacing\n- [x] Design A **compiler**, the compiler should provide higher level functionalities such as push/pop,mov etc.\n- [ ] Code a snake game\n- [ ] Design preset **bootloader** and **interrupt** set\n\n## The Project\n\nOpen the [CPU.circ](CPU.circ) file in [Logisim Evolution](https://github.com/logisim-evolution/logisim-evolution). Write assembly codes following the [Assembly Manual](assembly.md) and compile/assemble using the compiler (Requires [NodeJS](https://nodejs.org/en)).\n\n```bash\n./translate file.asm\n```\n\n\u003cfigure\u003e\n\u003cimg src=\"./assets/whole.png\"\u003e\n\u003ccaption\u003e The computer designed in Logisim Evolution\u003c/caption\u003e\n\u003c/figure\u003e\n\nThe details on the hardware design can be found [here](./design.md). Learn about the [Compiler Design](./compiler.md)\n\u003cbr\u003e\n\u003cbr\u003e\n\n## Notes\n\n- The r0 has a fixed value : 0 , which is useful for implementing various high level features such as mov or jz. The r16 produces random value.\n- In case of jumps the later 3 instructions must be replaced with nop\n- Cache was not added as it'd require interrupt management system and slow down the computer\n- No register on WB - Memory (As memory already takes one clock extra), May need to add buffer on every IO\n- While debugging hard errors can be detected by checking current status (line status); most hard errors are delay related. In case of soft error / resource conflict, it must be resolved by the assembler (pause command in case of conflict, if placable place other instruction else place nop).\n\n## References\n\n- [Wikipedia - RISC-V](https://en.wikipedia.org/wiki/RISC-V)\n- [The RISC-V Instruction Set Manual](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)\n- [Stack Overflow - How to implement CISC Pipeline](https://stackoverflow.com/questions/55454314/how-to-implement-cisc-pipelined-cpu-right)\n- [ResearchGate - RISC-V](https://www.researchgate.net/figure/Block-diagram-of-RISCV-SoC-and-its-five-stage-RISC-V-processor-Resources-from-different_fig3_363175823)\n- [Wikipedia - Clasic RISC Pipeline](https://en.wikipedia.org/wiki/Classic_RISC_pipeline)\n- [Berkeley - RISC-V CPU Control, Pipelining](https://inst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture12.pdf)\n- [RISC-V Pipeline\n  Implementation](https://passlab.github.io/CSCE513/notes/lecture08_RISCV_Impl_pipeline.pdf)\n- [Cornell - RISC-V Interpreter](https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/interpreter/)\n- [Washington - Pipelining](https://courses.cs.washington.edu/courses/cse378/10sp/lectures/lec11.pdf)\n- [FSU - Pipelined Datapath](https://www.cs.fsu.edu/~zwang/files/cda3101/Fall2017/Lecture8_cda3101.pdf)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftasmirz%2Fcomputer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftasmirz%2Fcomputer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftasmirz%2Fcomputer/lists"}