{"id":22254041,"url":"https://github.com/teddy-van-jerry/ngspice-cmos","last_synced_at":"2026-02-16T07:32:29.748Z","repository":{"id":171381708,"uuid":"647780315","full_name":"Teddy-van-Jerry/ngspice-cmos","owner":"Teddy-van-Jerry","description":"NGSPICE Simulation of CMOS Circuits","archived":false,"fork":false,"pushed_at":"2023-06-06T15:32:11.000Z","size":1347,"stargazers_count":14,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-10-11T09:12:51.489Z","etag":null,"topics":["cmos","hspice","mos","ngspice","simulation","spice"],"latest_commit_sha":null,"homepage":"https://spice.tvj.one","language":"TeX","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Teddy-van-Jerry.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-05-31T14:00:52.000Z","updated_at":"2025-07-07T10:39:45.000Z","dependencies_parsed_at":null,"dependency_job_id":"76126444-46b3-47b8-941a-c04820e2d8b4","html_url":"https://github.com/Teddy-van-Jerry/ngspice-cmos","commit_stats":null,"previous_names":["teddy-van-jerry/ngspice-cmos"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Teddy-van-Jerry/ngspice-cmos","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Teddy-van-Jerry%2Fngspice-cmos","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Teddy-van-Jerry%2Fngspice-cmos/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Teddy-van-Jerry%2Fngspice-cmos/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Teddy-van-Jerry%2Fngspice-cmos/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Teddy-van-Jerry","download_url":"https://codeload.github.com/Teddy-van-Jerry/ngspice-cmos/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Teddy-van-Jerry%2Fngspice-cmos/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29502934,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-16T05:57:17.024Z","status":"ssl_error","status_checked_at":"2026-02-16T05:56:49.929Z","response_time":115,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cmos","hspice","mos","ngspice","simulation","spice"],"created_at":"2024-12-03T07:21:51.630Z","updated_at":"2026-02-16T07:32:29.722Z","avatar_url":"https://github.com/Teddy-van-Jerry.png","language":"TeX","funding_links":[],"categories":[],"sub_categories":[],"readme":"# NGSPICE Simulation of CMOS Circuits \u003c!-- omit in toc --\u003e\n\n- GitHub: [Teddy-van-Jerry/ngspice-cmos](https://github.com/Teddy-van-Jerry/ngspice-cmos)\n- Website: [spice.tvj.one](https://spice.tvj.one)\n- PDF Report: [`NGSPICE_CMOS_Report.pdf`](report/NGSPICE_CMOS_Report.pdf)\n\n**Table of Contents**\n- [Summary](#summary)\n- [Environments](#environments)\n  - [Preparation](#preparation)\n  - [Settings](#settings)\n  - [Development](#development)\n- [Definitions](#definitions)\n- [Sources](#sources)\n  - [`FreePDK45/`](#freepdk45)\n  - [Inverter](#inverter)\n    - [Design](#design)\n    - [Simulation](#simulation)\n  - [NAND2](#nand2)\n    - [Design](#design-1)\n    - [Simulation](#simulation-1)\n  - [AND2](#and2)\n  - [NOR2](#nor2)\n    - [Design](#design-2)\n    - [Simulation](#simulation-2)\n  - [AND8](#and8)\n    - [Basic Components](#basic-components)\n    - [AND8A (Symmetrical Design)](#and8a-symmetrical-design)\n    - [AND8B (NAND4A \\* 2 + NOR2 \\* 1)](#and8b-nand4a--2--nor2--1)\n    - [AND8C (AND4B \\* 2 + AND2 \\* 1)](#and8c-and4b--2--and2--1)\n    - [Analysis](#analysis)\n  - [Clock Controlled SR Latch](#clock-controlled-sr-latch)\n    - [Schematic Design](#schematic-design)\n    - [MOS W/L Design](#mos-wl-design)\n    - [Simulation](#simulation-3)\n- [License](#license)\n\n## Summary\nNGSPICE is a powerful open-source SPICE simulation software in command line,\nwhich can efficiently simulate CMOS circuits.\nBasic logic gates, including NOT, NAND, AND, NOR, are implemented and analyzed.\nThe delay parameters and response plots can help understand the circuit characteristics.\nAs examples, the 8-input NAND gate with three distinct designs is investigated,\nand the clock controlled SR latch is also simulated to design appropriate MOS parameters.\n\n\u003e **Note** This is the course project of *Fundamentals of VLSI Design*, Southeast University, 2023 Spring.\n\n## Environments\n### Preparation\nInstall [NGSPICE](https://ngspice.sourceforge.io/) CLI app.\nThe schematic plot and the PDF report requires installation of LaTeX.\n\n### Settings\nNGSPICE is set to be compatible with HSPICE (see [`.spiceinit`](.spiceinit)).\n\n### Development\nMy development environments:\n- macOS 13 (Ventura) with M1 chip\n- NGSPICE 40 (Homebrew version)\n\n\u003e **Warning** There is *no* guarantee that the provided code can run on other platforms or other SPICE tools.\n\u003e Make changes if appropriate.\n\n## Definitions\nDelay:\n- **tr**: rise time (from output crossing 0.1 VDD to 0.9 VDD)\n- **tf**: fall time (from output crossing 0.9 VDD to 0.1 VDD)\n- **tpdr**: rising propagation delay (from input to rising output crossing VDD/2)\n- **tpdf**: falling propagation delay (from input to falling output crossing VDD/2)\n- **tpd**: average propagation delay (tpd = (tpdr + tpdf)/2)\n\nOperating corner:\n- **SS**: slow-slow\n- **NOM**: nominal (average)\n- **FF**: fast-fast\n\n## Sources\n### `FreePDK45/`\nThis is a 45nm CMOS library.\nSee [README](FreePDK45/README) for more information.\n\n`TNOM` is 27C.\n\n### Inverter\nInverter with 1 PMOS and 1 NMOS.\n(Design Requirement: tr = tf when CL = 24fF)\n\n- [`inv.inc`](inv.inc) is the `subckt` design;\n- [`inv.cir`](inv.cir) is the CMOS inverter simulation.\n\n#### Design\n\n**Schematic**\n\n![CMOS Inverter Schematic](fig/inv_schematic.svg)\n\n**Designed MOS Parameters**\n\n|  MOS  |   W   |   L   |\n| :---: | :---: | :---: |\n| PMOS  | 360nm | 45nm  |\n| NMOS  | 225nm | 45nm  |\n\ntr = 119ps, tf = 120ps, tpdr = 60ps, tpdf = 64ps, tpd = 62ps.\n\n**Source** [`inv.inc`](inv.inc)\n\n```spice\n.subckt INV gnd i o vdd\n  *  src  gate drain body type\n  M1 vdd  i    o     vdd  PMOS_VTL W=360nm L=45nm\n  M2 gnd  i    o     gnd  NMOS_VTL W=225nm L=45nm\n.ends INV\n```\n\n#### Simulation\n\nSimulate with\n```shell\nngspice inv.cir\n```\n\n**Response**\n\n![CMOS Inverter Response](fig/plot_inv_t.svg)\n\n### NAND2\n\n#### Design\nThe CMOS NAND2 gate is symmetrically designed with parameters for the worst case.\n\n**Schematic**\n\n![CMOS NAND2 Gate Schematic](fig/nand2_schematic.svg)\n\n**Designed MOS Parameters**\n\n|  MOS  | Num |   W   |   L   |\n| :---: | :-: | :---: | :---: |\n| PMOS  |  2  | 360nm | 45nm  |\n| NMOS  |  2  | 450nm | 45nm  |\n\n**Source** [`nand2.inc`](nand2.inc)\n\n```spice\n.subckt NAND2 gnd i1 i2 o vdd\n  *   src  gate drain body type\n  Mp1 vdd  i1   o     vdd  PMOS_VTL W=360nm L=45nm\n  Mp2 vdd  i2   o     vdd  PMOS_VTL W=360nm L=45nm\n  Mn1 t1   i1   o     gnd  NMOS_VTL W=450nm L=45nm\n  Mn2 gnd  i2   t1    gnd  NMOS_VTL W=450nm L=45nm\n.ends NAND2\n```\n\n#### Simulation\n\nThe worst case is simulated. Simulate with\n```shell\nngspice nand2.cir\n```\n\n**Response**\n\n![CMOS NAND2 Response](fig/plot_nand2_t.svg)\n\n### AND2\n\nAND2 is [NAND2](#nand2) + [INV](#inverter).\n\nSimulate with\n```shell\nngspice and2.cir\n```\n\n**Response**\n\n![CMOS AND2 Response](fig/plot_and2_t.svg)\n\n### NOR2\n\n#### Design\n\n**Schematic**\n\n![CMOS NOR2 Gate Schematic](fig/nor2_schematic.svg)\n\n**Source** [`nor2.inc`](nor2.inc)\n```spice\n.subckt NOR2 gnd i1 i2 o vdd\n  *   src  gate drain body type\n  Mp1 t1   i1   o     vdd  PMOS_VTL W=720nm L=45nm\n  Mp2 vdd  i2   t1    vdd  PMOS_VTL W=720nm L=45nm\n  Mn1 gnd  i1   o     gnd  NMOS_VTL W=225nm L=45nm\n  Mn2 gnd  i2   o     gnd  NMOS_VTL W=225nm L=45nm\n.ends NOR2\n```\n\n#### Simulation\n\nSimulate with\n```shell\nngspice nor2.cir\n```\n\n**Response**\n\n![CMOS NOR2 Response](fig/plot_nor2_t.svg)\n\n### AND8\n\n8-input AND gate.\nWith a large fan-in, there can be several designs.\nHere we want to investigate the performance of different designs.\n\nThe test circuit (defined in [add8_test_inv2.inc](add8_test_inv2.inc))\ninvolves a 24fF capacitor load at the output,\nand 8 sets of two stages of inverters for each input.\nFor the inverter in the test circuit,\nNMOS has W = 0.75um, L = 0.25um,\nand PMOS has W = 2.60um, L = 0.25um.\n\nThe response simulation has the PVT condition of 1.0V, FF, 25°C.\n\n#### Basic Components\n\n##### NAND4A \u003c!-- omit in toc --\u003e\nThis directly extends the structure of NAND2 into NAND4.\n\n![CMOS NAND4A Gate Schematic](fig/nand4_schematic.svg)\n\n##### NAND8A \u003c!-- omit in toc --\u003e\nThis directly extends the structure of NAND2 into NAND8.\n\n![CMOS NAND8A Gate Schematic](fig/nand8_schematic.svg)\n\n#### AND8A (Symmetrical Design)\n\nThis is the most basic case, extending 2-input NAND to 8-input NAND,\nbefore applying an inverter.\n\n**Schematic**\n\n![CMOS AND8A Gate Schematic](fig/and8a_schematic.svg)\n\n|  PVT Condition  | tr (ps) | tf (ps) | tpdr (ps) | tpdf (ps) | P static (uW) | P dynamic (uW) |\n|:---------------:|:-------:|:-------:|:---------:|:---------:|:-------------:|:--------------:|\n|  0.9V, SS, 70°C |  132.6  |  136.9  |   137.3   |   159.9   |     0.076     |      2.366     |\n| 1.35V, SS, 70°C |  110.6  |  124.4  |   102.4   |   125.9   |     1.023     |      5.591     |\n| 1.0V, NOM, 25°C |   90.5  |   99.2  |    83.8   |   110.5   |     0.227     |      2.733     |\n| 1.5V, NOM, 25°C |   79.8  |   95.0  |    69.4   |    92.4   |     6.566     |      9.669     |\n|  1.1V, FF, 0°C  |   72.5  |   84.6  |    62.7   |    89.4   |     0.955     |      5.321     |\n|  1.65V, FF, 0°C |   69.1  |   83.6  |    54.2   |    75.3   |     51.582    |      1.121     |\n\n**Response**\n\n![CMOS AND8A Response](fig/plot_and8a_t.svg)\n\n#### AND8B (NAND4A * 2 + NOR2 * 1)\n\n**Schematic**\n\n![CMOS AND8B Gate Schematic](fig/and8b_schematic.svg)\n\n|  PVT Condition  | tr (ps) | tf (ps) | tpdr (ps) | tpdf (ps) | P static (uW) | P dynamic (uW) |\n|:---------------:|:-------:|:-------:|:---------:|:---------:|:-------------:|:--------------:|\n|  0.9V, SS, 70°C |  118.8  |  131.7  |   102.8   |   106.2   |     0.030     |      2.233     |\n| 1.35V, SS, 70°C |   96.2  |  113.1  |    78.3   |    83.3   |     0.641     |      6.204     |\n| 1.0V, NOM, 25°C |   77.2  |   94.9  |    62.7   |    73.0   |     0.125     |      2.592     |\n| 1.5V, NOM, 25°C |   65.7  |   85.5  |    52.0   |    61.0   |     4.895     |     12.301     |\n|  1.1V, FF, 0°C  |   59.4  |   79.9  |    46.2   |    58.8   |     0.510     |      5.289     |\n|  1.65V, FF, 0°C |   53.3  |   74.3  |    30.5   |    50.3   |     43.767    |     11.248     |\n\n**Response**\n\n![CMOS AND8B Response](fig/plot_and8b_t.svg)\n\n#### AND8C (AND4B * 2 + AND2 * 1)\n\n**Schematic**\n\n![CMOS AND8C Gate Schematic](fig/and8c_schematic.svg)\n\n|  PVT Condition  | tr (ps) | tf (ps) | tpdr (ps) | tpdf (ps) | P static (uW) | P dynamic (uW) |\n|:---------------:|:-------:|:-------:|:---------:|:---------:|:-------------:|:--------------:|\n|  0.9V, SS, 70°C |  118.8  |  120.3  |   103.3   |   105.0   |     0.111     |      3.067     |\n| 1.35V, SS, 70°C |   96.7  |  102.6  |    79.8   |    83.5   |     1.253     |      9.458     |\n| 1.0V, NOM, 25°C |   81.5  |   86.9  |    68.4   |    73.3   |     0.301     |      4.164     |\n| 1.5V, NOM, 25°C |   69.1  |   77.8  |    56.6   |    62.4   |     8.471     |     16.348     |\n|  1.1V, FF, 0°C  |   65.0  |   73.0  |    53.6   |    60.0   |     1.175     |      6.652     |\n|  1.65V, FF, 0°C |   47.9  |   67.8  |    46.9   |    52.2   |     73.357    |     20.798     |\n\n**Response**\n\n![CMOS AND8C Response](fig/plot_and8c_t.svg)\n\n#### Analysis\nAmong the three designs ([AND8A](#and8a-symmetrical-design), [AND8B](#and8b-nand4a--2--nor2--1) and [AND8C](#and8c-and4b--2--and2--1)),\n[AND8B](#and8b-nand4a--2--nor2--1) has the smallest latency,\nclosely followed by [AND8c](#and8c-and4b--2--and2--1),\nand the largest latency is observed with [AND8A](#and8a-symmetrical-design).\nCompared with [AND8A](#and8a-symmetrical-design), the fan-in of [AND8B](#and8b-nand4a--2--nor2--1) is significantly reduced,\nresulting in lower latency.\nThough [AND8C](#and8c-and4b--2--and2--1) has an even smaller fan-in, the number of stages in the circuit is larger than that of [AND8B](#and8b-nand4a--2--nor2--1).\nThus, [AND8B](#and8b-nand4a--2--nor2--1) achieves a reasonable tradeoff, and has the lowest latency.\n\nThere are also some other observations:\n- A larger VDD can reduce the latency to some extent, but resulting in much larger power consumption.\n- A faster operating corner (FF \u003e NOM \u003e SS) will help cut down latency, but also increases power.\n- A higher temperature increases power in return for a reduced latency.\n\n### Clock Controlled SR Latch\n\n#### Schematic Design\n\n2 PMOS + 6 NMOS\n\n![Clock Controlled SR Latch Schematic](fig/SR_latch_clk_schematic.svg)\n\n**Source** [`SR_latch_clk.inc`](SR_latch_clk.inc)\n```spice\n* .param WL = 5\n.subckt SR_LATCH_CLK gnd s r clk q qn vdd\n  *  src  gate drain body type\n  M1 qn   q    gnd   gnd  NMOS_VTL W=     90nm L=45nm\n  M2 qn   q    vdd   vdd  PMOS_VTL W=    270nm L=45nm\n  M3 q    qn   gnd   gnd  NMOS_VTL W=     90nm L=45nm\n  M4 q    qn   vdd   vdd  PMOS_VTL W=    270nm L=45nm\n  M5 ts   s    gnd   gnd  NMOS_VTL W={WL*45nm} L=45nm\n  M6 qn   clk  ts    gnd  NMOS_VTL W={WL*45nm} L=45nm\n  M7 tr   r    gnd   gnd  NMOS_VTL W={WL*45nm} L=45nm\n  M8 q    clk  tr    gnd  NMOS_VTL W={WL*45nm} L=45nm\n.ends SR_LATCH_CLK\n```\nYou need to specify the parameter `WL`, for example `.param WL = 5`.\n\n#### MOS W/L Design\n\nWe need to determine the appropriate W/L for `M5` to `M8`.\nUsing a sweep, implemented by `alterparam` within a `foreach` loop,\nwe can obtain the following graph.\n\n![Clock Controlled SR Latch with Different W/L](fig/plot_sr_latch_wl_t.svg)\n\nClearly, we need W/L \u003e 4.5 (at least 4.2) for the latch to work properly.\n(`M1`/`M3` and `M2`/`M4` have W/L as 2 and 6, respectively.)\n\n#### Simulation\n\n```sh\nngspice SR_latch_clk.cir\n```\n\n**Response**\n\n![Clock Controlled SR Latch](fig/plot_sr_latch_t.svg)\n\n## License\nCopyright (C) 2023 Wuqiong Zhao (me@wqzhao.org)\n\nThis project is distributed by an [MIT license](LICENSE).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fteddy-van-jerry%2Fngspice-cmos","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fteddy-van-jerry%2Fngspice-cmos","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fteddy-van-jerry%2Fngspice-cmos/lists"}