{"id":26397310,"url":"https://github.com/thalesgroup/udp-offload-engine","last_synced_at":"2025-10-09T14:08:20.834Z","repository":{"id":78566469,"uuid":"485790190","full_name":"ThalesGroup/udp-offload-engine","owner":"ThalesGroup","description":"UDP-IP stack accelerator and is able to send and receive data through Ethernet link","archived":false,"fork":false,"pushed_at":"2025-02-23T23:57:59.000Z","size":1614,"stargazers_count":24,"open_issues_count":1,"forks_count":5,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-06-14T09:05:08.688Z","etag":null,"topics":["ethernet","fpga","ip","udp","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ThalesGroup.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":"SECURITY.md","support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2022-04-26T13:07:04.000Z","updated_at":"2025-06-11T03:00:59.000Z","dependencies_parsed_at":"2023-03-02T19:00:17.232Z","dependency_job_id":"7aaff443-af93-46f0-bcae-090563535ea7","html_url":"https://github.com/ThalesGroup/udp-offload-engine","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":"ThalesGroup/template-project","purl":"pkg:github/ThalesGroup/udp-offload-engine","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ThalesGroup%2Fudp-offload-engine","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ThalesGroup%2Fudp-offload-engine/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ThalesGroup%2Fudp-offload-engine/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ThalesGroup%2Fudp-offload-engine/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ThalesGroup","download_url":"https://codeload.github.com/ThalesGroup/udp-offload-engine/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ThalesGroup%2Fudp-offload-engine/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":259790456,"owners_count":22911547,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ethernet","fpga","ip","udp","vhdl"],"created_at":"2025-03-17T12:17:21.633Z","updated_at":"2025-10-09T14:08:20.764Z","avatar_url":"https://github.com/ThalesGroup.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# udp-offload-engine\n\n![logo](docs/logo/uoe_300x206.png)\n\n## Get started\n\nThe UDP Offload Engine is an IP VHDL used for FPGA hardware programming.\n\nThis IP is an UDP-IP stack accelerator and is able to send and receive data through Ethernet link.\nThis stack is highly configurable to be used with Ethernet rates up to 40Gb/s thanks to its configurable bus size.\nMoreover it is modular. It implements different protocols and integrated testing tools that can be deactivated in order to save resources.\n\nThis IP is based on Building Blocks following the Thales Strategy in engineering. They perform basic functions and allow to be independent from the platform/target.\nNo manufacturer primitive are used on this design, all are inferred.\n\n*******\nTables of contents  \n 1. [Documentation](#documentation)\n 2. [Key points](#keypoints)\n 3. [Performances](#performances)\n 4. [Design example](#designexample)\n 5. [Roadmap](#roadmap)\n 6. [Contributing](#contributing)\n 7. [License](#license)\n \n*******\n\n\u003cdiv id='documentation'/\u003e \n\n## Documentation\n\n![uoe](docs/schematics/UOE_functional_scheme.png)\n\nThis figure describe the internal architecture of the IP. \nThe main entity is the module **_uoe_core_**. \nIt was encapsulated in a top wrapper **_top_uoe_** which additionally instantiate some integrated tests functions.\n\n* Functional part\n\n  * Link layer : Lower layer of the IP, it allows the connection with the MAC layer. It handle the Ethernet protocol, directs incoming packets and can filter them.\n  * Internet layer : It is the intermediate layer which handle the IPv4 Protocol and a part of ICMP Protocol (Ping)\n  * Transport layer : This layer is dedicated to the UDP protocol\n  \n* Built-In-Test part (Optional)\n\n  * On the main interfaces of the stack (MAC and UDP), two LoopBack fifos have been implemented\n  * On the UDP Side, a generator/checker has been integrated for debugging.\n  \nThe Full documentation of the stack is available on the [architecture guide](docs/architecture.md).\n\n\u003cdiv id='keypoints'/\u003e \n\n## Key points\n\n* Configurable bus size\n\n* Handle the following protocols\n\n  * User Datagram Protocol (UDP)\n  * Internet Protocol version 4 (IPv4)\n    * Fragmentation support\n    \n* Address Resolution Protocol (ARP)\n\n  * Handle of ARP Table\n  * IP/MAC address conflict detection\n\n* Internet Control Message Procotol (ICMP)\n\n  * Echo Request/Reply (PING) (Coming soon...)\n  \n* Take into account buffers on the MAC interface and clock domain crossing\n\n* Filtering option for incoming traffic\n\n* Use of standard bus\n\n  * Data link in AXI4-Stream \n  * Control link in AXI4-Lite 32 bits\n  \n\u003cdiv id='performances'/\u003e \n  \n## Performances\n\nThe design has been synthesized and implemented with different generics parameters and for several target in out of context. Result are available on the [Performance page](docs/performances.md).\n  \n\u003cdiv id='designexample'/\u003e\n\n## Design example\n\nThis repo integrate the following design example :\n\n* AMD-Xilinx FPGA: on KCU105 EvalBoard\n  \n\u003cdiv id='roadmap'/\u003e\n\n## Roadmap\n\nComing soon ...\n\n\u003cdiv id='contributing'/\u003e\n\n## Contributing\n\nIf you are interested in contributing to this project, start by reading the [Contributing guidelines](/CONTRIBUTING.md).\n\n\u003cdiv id='license'/\u003e\n\n## License\n\n* [Apache License, Version 2.0](LICENSE) \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthalesgroup%2Fudp-offload-engine","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fthalesgroup%2Fudp-offload-engine","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthalesgroup%2Fudp-offload-engine/lists"}