{"id":22134131,"url":"https://github.com/theveryhim/fpga-course-project","last_synced_at":"2025-03-24T09:42:48.319Z","repository":{"id":265742748,"uuid":"869990392","full_name":"theveryhim/FPGA-Course-Project","owner":"theveryhim","description":"Signal processing using Zynq7000 Board(AX7010)","archived":false,"fork":false,"pushed_at":"2025-02-20T22:33:39.000Z","size":99493,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-20T23:24:44.106Z","etag":null,"topics":["c","matlab","signal-processing","verilog-hdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/theveryhim.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-10-09T08:53:25.000Z","updated_at":"2025-02-20T22:33:42.000Z","dependencies_parsed_at":"2024-11-30T19:30:43.254Z","dependency_job_id":"f2c12160-880a-4468-a299-b52dcf72927c","html_url":"https://github.com/theveryhim/FPGA-Course-Project","commit_stats":null,"previous_names":["theveryhim/fpga-course-project"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/theveryhim%2FFPGA-Course-Project","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/theveryhim%2FFPGA-Course-Project/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/theveryhim%2FFPGA-Course-Project/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/theveryhim%2FFPGA-Course-Project/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/theveryhim","download_url":"https://codeload.github.com/theveryhim/FPGA-Course-Project/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":245248137,"owners_count":20584478,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c","matlab","signal-processing","verilog-hdl"],"created_at":"2024-12-01T19:09:35.321Z","updated_at":"2025-03-24T09:42:43.305Z","avatar_url":"https://github.com/theveryhim.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"This is a simple signal processing project on Zynq which includes:\n  - Introduction to Scrambler and Descrambler\n  - Introduction to FFT and displaying the spectrum of digital signals via HDMI on the display\n![Overview of project](https://github.com/user-attachments/assets/e7c73c87-2a06-4fa6-85f6-3a38b8a34664)\n\n**Project describtion is provided in FPGA_Project_Draft(persian) but reports are adequate to read in English!**\n\n## Stage 1:\nIn this phase, we initially create four types of square, sawtooth, triangular, and sine waves \nin PS (each with 1024 samples, 8-bit). You transfer this signal to PL through the HP port with \nthe appropriate configuration for DMA. By pressing 1KEY_PS, the sent signal to the FPGA changes \nbetween the four created signals.\n\nRelated Documents:\n  - [Vivado project file](https://www.dropbox.com/scl/fo/mbf7uec3n0lks7kfpmr7v/AB-lu52Xzw_MyFjoZeSUaDY?rlkey=t8ngle1a1tjvpvgnyj29x9w6w\u0026st=9xh5f244\u0026dl=0)\n  - Report01\n## Stage 2:\nIn this satge, a conventional ASM structure is added along with a Scrambler. In fact,in this project\nwe will implement a transmitter in the PS section and a receiver in the PL section.\nWe use the DS/CCS header or send multiple samples as a header and wait to receive it at the receiver\nto reset our Descrambler.\n\nRelated Document:\n  - Files:\n    - C\n    - Verilog\n    - Matlab\n  - Report:\n    - Report02\n     \n*July 2024* \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftheveryhim%2Ffpga-course-project","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftheveryhim%2Ffpga-course-project","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftheveryhim%2Ffpga-course-project/lists"}