{"id":24495133,"url":"https://github.com/thomasafroo/simple-risc-machine","last_synced_at":"2025-03-15T04:42:57.039Z","repository":{"id":260996242,"uuid":"882939074","full_name":"thomasafroo/Simple-RISC-Machine","owner":"thomasafroo","description":"Implements a RISC processor that executes a set of ARMv7 instructions.","archived":false,"fork":false,"pushed_at":"2025-01-12T20:25:13.000Z","size":430,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-21T20:19:00.565Z","etag":null,"topics":["risc","simulation","synthesis","systemverilog"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/thomasafroo.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-11-04T04:40:53.000Z","updated_at":"2025-01-12T21:14:50.000Z","dependencies_parsed_at":null,"dependency_job_id":"703e5cda-ea52-46bc-bbb2-b1d53bcdaed1","html_url":"https://github.com/thomasafroo/Simple-RISC-Machine","commit_stats":null,"previous_names":["thomasafroo/riscmachine","thomasafroo/risc-machine-project"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FSimple-RISC-Machine","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FSimple-RISC-Machine/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FSimple-RISC-Machine/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FSimple-RISC-Machine/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/thomasafroo","download_url":"https://codeload.github.com/thomasafroo/Simple-RISC-Machine/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243685528,"owners_count":20330980,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["risc","simulation","synthesis","systemverilog"],"created_at":"2025-01-21T20:19:03.387Z","updated_at":"2025-03-15T04:42:56.984Z","avatar_url":"https://github.com/thomasafroo.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Simple RISC Machine\n\nThis project implements a Reduced Instruction Set Computer (RISC) using SystemVerilog and can be tested using the Intel DE1-SoC development board.\nThe RISC machine can execute a set of instructions from the ARMv7 Instruction Set Architecture (ISA). It contains a datapath, finite state machine controller, and support for read-write memory.\n\nThis project was done in collaboration with my lab partner, Jackson Rockford, for CPEN 211: Introduction to Microcomputers.\n\nImportant: viewers should be mindful of the Academic Integrity Policy for CPEN 211 and UBC ECE.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthomasafroo%2Fsimple-risc-machine","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fthomasafroo%2Fsimple-risc-machine","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthomasafroo%2Fsimple-risc-machine/lists"}