{"id":24495135,"url":"https://github.com/thomasafroo/uvm-based-verification-of-4-bit-adder","last_synced_at":"2026-02-06T04:31:18.026Z","repository":{"id":271060998,"uuid":"912295206","full_name":"thomasafroo/UVM-Based-Verification-of-4-Bit-Adder","owner":"thomasafroo","description":"A combinational adder project that contains verification in UVM.","archived":false,"fork":false,"pushed_at":"2025-01-12T22:44:51.000Z","size":39,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-15T04:44:12.388Z","etag":null,"topics":["systemverilog","uvm"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/thomasafroo.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-01-05T06:42:20.000Z","updated_at":"2025-01-12T22:44:55.000Z","dependencies_parsed_at":"2025-03-20T00:00:39.512Z","dependency_job_id":null,"html_url":"https://github.com/thomasafroo/UVM-Based-Verification-of-4-Bit-Adder","commit_stats":null,"previous_names":["thomasafroo/uvm_projects","thomasafroo/uvm-based-verification-of-4-bit-adder"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/thomasafroo/UVM-Based-Verification-of-4-Bit-Adder","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FUVM-Based-Verification-of-4-Bit-Adder","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FUVM-Based-Verification-of-4-Bit-Adder/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FUVM-Based-Verification-of-4-Bit-Adder/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FUVM-Based-Verification-of-4-Bit-Adder/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/thomasafroo","download_url":"https://codeload.github.com/thomasafroo/UVM-Based-Verification-of-4-Bit-Adder/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thomasafroo%2FUVM-Based-Verification-of-4-Bit-Adder/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29150609,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-06T02:39:25.012Z","status":"ssl_error","status_checked_at":"2026-02-06T02:37:22.784Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["systemverilog","uvm"],"created_at":"2025-01-21T20:19:03.472Z","updated_at":"2026-02-06T04:31:18.010Z","avatar_url":"https://github.com/thomasafroo.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# UVM-Based Verification of 4-Bit Adder\n\nThis project demonstrates the use of Universal Verification Methodology (UVM) to verify a 4-bit combinational adder design. The project contains the SystemVerilog design module, interface, and a comprehensive UVM-based testbench that verifies the functionality of the design using various verification components.\n\n## Project Structure\n\n### Design Module (`adder_4_bit.sv`)\n\nThe adder module performs a simple 4-bit addition and outputs the 5-bit result.\n\n```systemverilog\nmodule add(\n  input [3:0] a, b,\n  output [4:0] y\n);\n  assign y = a + b;\nendmodule\n```\n\n### Interface (`add_if`)\n\nThe interface connects the testbench with the design-under-test (DUT) by defining the input and output signals:\n\n```systemverilog\ninterface add_if();\n  logic [3:0] a;\n  logic [3:0] b;\n  logic [4:0] y;\nendinterface\n```\n\n### Testbench Structure\n\n#### Transaction\n\nThe `transaction` class represents data items (input and expected output) used during the test.\n```systemverilog\nclass transaction extends uvm_sequence_item;\n  rand bit [3:0] a;\n  rand bit [3:0] b;\n  bit [4:0] y;\n  \n    function new(input string path = \"transaction\");\n      super.new(path);\n    endfunction\n  \n  `uvm_object_utils_begin(transaction)\n    `uvm_field_int(a, UVM_DEFAULT)\n    `uvm_field_int(b, UVM_DEFAULT)\n    `uvm_field_int(y, UVM_DEFAULT)\n  `uvm_object_utils_end\nendclass\n\n```\n#### Generator\n\nThe `generator` creates random transactions and sends them to the driver.\n```systemverilog\nclass generator extends uvm_sequence #(transaction);\n  `uvm_object_utils(generator)\n  \n  transaction t;\n  integer i;\n  \n  function new(input string path = \"generator\");\n    super.new(path);\n  endfunction\n  \n  \n  virtual task body();\n    t = transaction::type_id::create(\"t\");\n    repeat(10) \n    begin\n      start_item(t);\n      t.randomize();\n      `uvm_info(\"GEN\",$sformatf(\"Data send to Driver a :%0d , b :%0d\",t.a,t.b), UVM_NONE);\n      finish_item(t);\n    end\n  endtask\nendclass\n```\n#### Driver\n\nThe `driver` applies the generated transactions to the DUT using the interface.\n\n```systemverilog\nclass driver extends uvm_driver #(transaction);\n  `uvm_component_utils(driver)\n \n  function new(input string path = \"driver\", uvm_component parent = null);\n    super.new(path, parent);\n  endfunction\n \n  transaction tc;\n  virtual add_if aif;\n\n  virtual function void build_phase(uvm_phase phase);\n    super.build_phase(phase);\n    tc = transaction::type_id::create(\"tc\");\n\n    if(!uvm_config_db #(virtual add_if)::get(this,\"\",\"aif\",aif)) \n      `uvm_error(\"DRV\",\"Unable to access uvm_config_db\");\n  endfunction\n \n  virtual task run_phase(uvm_phase phase);\n    forever begin\n      seq_item_port.get_next_item(tc);\n      aif.a \u003c= tc.a;\n      aif.b \u003c= tc.b;\n      `uvm_info(\"DRV\", $sformatf(\"Trigger DUT a: %0d ,b :  %0d\",tc.a, tc.b), UVM_NONE); \n      seq_item_port.item_done();\n      #10;\n    end\n  endtask\nendclass\n```\n#### Monitor\n\nThe `monitor` observes the DUT's outputs and sends them to the scoreboard for checking.\n```systemverilog\nclass monitor extends uvm_monitor;\n  `uvm_component_utils(monitor)\n  uvm_analysis_port #(transaction) send;\n \n  function new(input string path = \"monitor\", uvm_component parent = null);\n    super.new(path, parent);\n    send = new(\"send\", this);\n  endfunction\n \n  transaction t;\n  virtual add_if aif;\n \n  virtual function void build_phase(uvm_phase phase);\n  super.build_phase(phase);\n  t = transaction::type_id::create(\"t\");\n    \n  if(!uvm_config_db #(virtual add_if)::get(this,\"\",\"aif\",aif)) \n    `uvm_error(\"MON\",\"Unable to access uvm_config_db\");\n  endfunction\n \n  virtual task run_phase(uvm_phase phase);\n    forever begin\n      #10;\n      t.a = aif.a;\n      t.b = aif.b;\n      t.y = aif.y;\n      `uvm_info(\"MON\", $sformatf(\"Data send to Scoreboard a : %0d , b : %0d and y : %0d\", t.a,t.b,t.y), UVM_NONE);\n      send.write(t);\n    end\n  endtask\nendclass\n```\n#### Scoreboard\n\nThe `scoreboard` compares the DUT output with the expected output to verify correctness.\n```systemverilog\nclass scoreboard extends uvm_scoreboard;\n   `uvm_component_utils(scoreboard)\n \n  uvm_analysis_imp #(transaction,scoreboard) recv;\n \n  transaction tr;\n \n  function new(input string path = \"scoreboard\", uvm_component parent = null);\n    super.new(path, parent);\n    recv = new(\"recv\", this);\n  endfunction\n \n  virtual function void build_phase(uvm_phase phase);\n    super.build_phase(phase);\n    tr = transaction::type_id::create(\"tr\");\n  endfunction\n \n  virtual function void write(input transaction t);\n    tr = t;\n    `uvm_info(\"SCO\",$sformatf(\"Data rcvd from Monitor a: %0d , b : %0d and y : %0d\",tr.a,tr.b,tr.y), UVM_NONE);\n  \n    if(tr.y == tr.a + tr.b)\n      `uvm_info(\"SCO\",\"Test Passed\", UVM_NONE)\n    else\n      `uvm_info(\"SCO\",\"Test Failed\", UVM_NONE);\n   endfunction\nendclass\n```\n\n#### Agent\n\nThe `agent` encapsulates the driver, monitor, and sequencer to provide a reusable verification component.\n```systemverilog\nclass agent extends uvm_agent;\n  `uvm_component_utils(agent)\n  \n  function new(input string inst = \"AGENT\", uvm_component c);\n    super.new(inst, c);\n  endfunction\n  \n  monitor m;\n  driver d;\n  uvm_sequencer #(transaction) seqr;\n  \n  virtual function void build_phase(uvm_phase phase);\n    super.build_phase(phase);\n    m = monitor::type_id::create(\"m\",this);\n    d = driver::type_id::create(\"d\",this);\n    seqr = uvm_sequencer #(transaction)::type_id::create(\"seqr\",this);\n  endfunction\n  \n  virtual function void connect_phase(uvm_phase phase);\n    super.connect_phase(phase);\n    d.seq_item_port.connect(seqr.seq_item_export);\n  endfunction\nendclass\n```\n#### Environment\n\nThe `environment` connects the agent and scoreboard, providing the testbench structure.\n```systemverilog\nclass env extends uvm_env;\n  `uvm_component_utils(env)\n \n  function new(input string inst = \"ENV\", uvm_component c);\n    super.new(inst, c);\n  endfunction\n \n  scoreboard s;\n  agent a;\n \n  virtual function void build_phase(uvm_phase phase);\n    super.build_phase(phase);\n    s = scoreboard::type_id::create(\"s\",this);\n    a = agent::type_id::create(\"a\",this);\n  endfunction\n \n  virtual function void connect_phase(uvm_phase phase);\n    super.connect_phase(phase);\n    a.m.send.connect(s.recv);\n  endfunction\nendclass\n```\n#### Test\n\nThe `test` defines the test sequence and initiates the verification process.\n```systemverilog\nclass test extends uvm_test;\n  `uvm_component_utils(test)\n  \n  function new(input string inst = \"TEST\", uvm_component c);\n    super.new(inst, c);\n  endfunction\n  \n  generator gen;\n  env e;\n  \n  virtual function void build_phase(uvm_phase phase);\n    super.build_phase(phase);\n    gen = generator::type_id::create(\"gen\");\n    e = env::type_id::create(\"e\",this);\n  endfunction\n  \n  virtual task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    gen.start(e.a.seqr);\n    #50;\n    phase.drop_objection(this);\n  endtask\nendclass\n```\n### Top-Level Testbench Module (`adder_4_bit_tb.sv`)\n\nThe top-level module instantiates the DUT and interface and runs the UVM test.\n```systemverilog\nmodule add_tb();\n  add_if aif();\n  add dut (.a(aif.a), .b(aif.b), .y(aif.y));\n\n  initial begin\n    $dumpfile(\"dump.vcd\");\n    $dumpvars;\n  end\n    \n  initial begin  \n    uvm_config_db #(virtual add_if)::set(null, \"uvm_test_top.e.a*\", \"aif\", aif);\n    run_test(\"test\");\n  end\nendmodule\n```\n## How to Run\n\n1. **Requirements:**\n- EDA Playground supporting SystemVerilog and UVM with Aldec Riviera Pro\n  - [View on EDA Playground](https://edaplayground.com/x/tb4f)\n\n## Features\n\n- **UVM Components:** Full utilization of UVM components (transaction, driver, monitor, scoreboard, etc.).\n- **Randomization:** Randomized input generation to stress-test the design.\n- **Coverage:** Functional coverage through monitored transactions.\n- **Reusability:** Modular and reusable verification components.\n\n## Verification Flow\n\n1. The generator produces random input transactions.\n2. The driver applies these transactions to the DUT.\n3. The monitor captures the DUT outputs.\n4. The scoreboard checks if the DUT output matches the expected values.\n5. Results are logged, and the test passes or fails based on the comparison.\n\n## Example Simulation Log\n\n```\nUVM_INFO @ 0: GEN: Data sent to Driver a: 5, b: 3\nUVM_INFO @ 10: DRV: Trigger DUT a: 5, b: 3\nUVM_INFO @ 20: MON: Data sent to Scoreboard a: 5, b: 3, y: 8\nUVM_INFO @ 20: SCO: Test Passed\n```\n\n## Future Work\n\n- Extend verification for corner cases (e.g., overflow).\n- Add functional and code coverage reports.\n- Parameterize the design for variable bit widths (e.g. 8-bit, 16-bit)\n\n## References\n\n- [UVM Reference Manual](https://www.accellera.org/)\n- [SystemVerilog Language Reference](https://www.ieee.org/)\n\n---\n\nFeel free to reach out for any questions or suggestions regarding this project!\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthomasafroo%2Fuvm-based-verification-of-4-bit-adder","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fthomasafroo%2Fuvm-based-verification-of-4-bit-adder","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthomasafroo%2Fuvm-based-verification-of-4-bit-adder/lists"}