{"id":21442254,"url":"https://github.com/thotypous/keccak-bsv","last_synced_at":"2026-03-19T20:25:59.727Z","repository":{"id":69726808,"uuid":"48628387","full_name":"thotypous/keccak-bsv","owner":"thotypous","description":"Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3)","archived":false,"fork":false,"pushed_at":"2015-12-27T22:12:19.000Z","size":215,"stargazers_count":2,"open_issues_count":0,"forks_count":2,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-06-18T17:48:48.708Z","etag":null,"topics":["bluespec","cryptography","hardware-designs","keccak","sha3"],"latest_commit_sha":null,"homepage":null,"language":"Bluespec","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/thotypous.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2015-12-27T01:00:32.000Z","updated_at":"2023-05-09T06:20:13.000Z","dependencies_parsed_at":"2023-03-13T20:24:53.797Z","dependency_job_id":null,"html_url":"https://github.com/thotypous/keccak-bsv","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/thotypous/keccak-bsv","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thotypous%2Fkeccak-bsv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thotypous%2Fkeccak-bsv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thotypous%2Fkeccak-bsv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thotypous%2Fkeccak-bsv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/thotypous","download_url":"https://codeload.github.com/thotypous/keccak-bsv/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/thotypous%2Fkeccak-bsv/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28966803,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-01T02:14:24.993Z","status":"ssl_error","status_checked_at":"2026-02-01T02:13:55.706Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["bluespec","cryptography","hardware-designs","keccak","sha3"],"created_at":"2024-11-23T01:53:14.294Z","updated_at":"2026-02-01T03:37:59.902Z","avatar_url":"https://github.com/thotypous.png","language":"Bluespec","funding_links":[],"categories":[],"sub_categories":[],"readme":"# keccak-bsv\n\nThis is an almost literal translation of\n[Keccak's reference VHDL implementation](http://keccak.noekeon.org/KeccakVHDL-3.1.zip)\nmid-range core to the Bluespec SystemVerilog (BSV) language. Our goals are:\n\n * Easier integration with Bluespec and/or Verilog projects, specially when simulating with\n   iverilog, whose support for mixed VHDL/Verilog simulation is still at early stages.\n\n * Be easier to understand and customize. As Bluespec is more flexible for static elaboration\n   than VHDL, our code is more compact although it implements the same architecture.\n\n## Building\n\nTyping `make` will test the implementation against the test vectors (using Bluesim) and\nsubsequently build the `mkKeccak.v` hardware core.\n\n## Synthesis comparison\n\nTo prove that our implementation is equivalent to the reference implementation,\nwe synthesized both implementations (for NumSlices=32) several times targeting an\nAltera Cyclone V device (5CSEMA5F31C6), varying the Quartus II fitter seed each time.\nThe figure below presents histograms for the clock frequency and logic utilization\nobtained by each implementation.\n\n![Synthesis results](http://thotypous.github.io/keccak-bsv/synthesis.svg)\n\nThe reference implementation (VHDL) tends to achieve a slightly higher clock frequency,\nwhereas our implementation (BSV) occupies somewhat less area. Overall, both\nimplementations produce similar results, as expected.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthotypous%2Fkeccak-bsv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fthotypous%2Fkeccak-bsv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fthotypous%2Fkeccak-bsv/lists"}