{"id":19358882,"url":"https://github.com/tiesen243/hdl","last_synced_at":"2026-03-19T09:27:07.752Z","repository":{"id":258942583,"uuid":"873729146","full_name":"tiesen243/hdl","owner":"tiesen243","description":null,"archived":false,"fork":false,"pushed_at":"2025-04-24T06:18:31.000Z","size":8368,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-05T06:49:10.720Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/tiesen243.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-10-16T16:08:26.000Z","updated_at":"2025-04-24T06:18:35.000Z","dependencies_parsed_at":"2025-04-17T14:21:02.229Z","dependency_job_id":"d9f71de9-84ed-465f-be89-27e44108f3e8","html_url":"https://github.com/tiesen243/hdl","commit_stats":null,"previous_names":["tiesen243/hdl","tiesen243/learn-hdl"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/tiesen243/hdl","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tiesen243%2Fhdl","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tiesen243%2Fhdl/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tiesen243%2Fhdl/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tiesen243%2Fhdl/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/tiesen243","download_url":"https://codeload.github.com/tiesen243/hdl/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tiesen243%2Fhdl/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29110568,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-05T03:44:17.043Z","status":"ssl_error","status_checked_at":"2026-02-05T03:44:12.077Z","response_time":65,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-10T07:13:24.361Z","updated_at":"2026-02-05T04:02:17.355Z","avatar_url":"https://github.com/tiesen243.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Verilog HDL Projects\n\nThis repository contains a collection of Verilog Hardware Description Language (HDL) projects designed to demonstrate various digital logic designs and concepts. The projects range from basic components like flip-flops and multiplexers to more complex systems such as finite state machines (FSMs) and digital clocks.\n\n## Table of Contents\n\n- [Overview](#overview)\n- [Project Structure](#project-structure)\n- [Getting Started](#getting-started)\n- [Prerequisites](#prerequisites)\n- [Usage](#usage)\n- [Contributing](#contributing)\n- [License](#license)\n\n## Overview\n\nThe projects within this repository are intended for educational purposes, providing practical examples of digital logic design using Verilog HDL. Each project is self-contained and focuses on a specific digital component or system, offering insights into design, simulation, and synthesis processes.\n\n## Project Structure\n\nThe repository is organized as follows:\n\n- `bcd_1/`, `bcd_2/`  \n\tProjects related to Binary-Coded Decimal (BCD) implementations.\n\n- `c2b/`, `c3b/`, `c4b/`  \n\tCode converters between different binary representations.\n\n- `clock_1/`, `clock_2/`  \n\tDigital clock designs with varying complexities.\n\n- `decoder4_16/`, `demux1_16/`  \n\tDecoder and demultiplexer implementations.\n\n- `flip_flop_1/`, `flip_flop_2/`, `flip_flop_3/`  \n\tVarious flip-flop designs demonstrating different triggering mechanisms.\n\n- `fsm_1/`, `fsm_2/`, `fsm_3/`  \n\tFinite State Machine designs showcasing different state transitions and outputs.\n\n- `func_1/`, `func_2/`  \n\tFunctional modules performing specific digital operations.\n\n- `led_7_seg/`, `led_7_seg_2/`  \n\tSeven-segment LED display controllers.\n\n- `multifier/`  \n\tMultiplier design for binary numbers.\n\n- `exercises/`  \n\tAdditional exercises and practice problems for reinforcing Verilog concepts.\n\n- `DE2_pin_assignments.csv`  \n\tPin assignment file for the DE2 development board.\n\n## Getting Started\n\nTo get started with any of the projects:\n\n1. Clone the repository:\n\n\t```bash\n\tgit clone https://github.com/tiesen243/hdl.git\n\t```\n\n2. Navigate to the project directory:\n\n\t```bash\n\tcd hdl\n\t```\n\n3. Open the desired project folder to access its Verilog source files.\n\n## Prerequisites\n\nEnsure you have the following tools installed on your development environment:\n\n- Verilog simulator (e.g., ModelSim)\n- Synthesis tool (e.g., Intel Quartus)\n- [Optional] DE2 development board for hardware implementation\n\n## Usage\n\nEach project folder contains Verilog source files (`.v`) that can be simulated and synthesized using the appropriate tools. Refer to the documentation within each folder for specific instructions on simulation and synthesis processes.\n\n## Contributing\n\nContributions are welcome! If you have suggestions for improvements or new projects to add, feel free to fork the repository and submit a pull request.\n\n## License\n\nThis repository is open-source and available under the [MIT License](LICENSE).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftiesen243%2Fhdl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftiesen243%2Fhdl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftiesen243%2Fhdl/lists"}