{"id":24281085,"url":"https://github.com/tommythorn/reduceron","last_synced_at":"2025-05-16T00:00:26.934Z","repository":{"id":43946187,"uuid":"1933823","full_name":"tommythorn/Reduceron","owner":"tommythorn","description":"FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection.  Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA.  A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. 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Reduceron has been\nimplemented on various FPGAs with clock frequency ranging from 60 to 150\nMHz depending on the FPGA.  A high degree of parallelism allows Reduceron\nto implement graph evaluation very efficiently.\n\nReduceron is the work of Matthew Naylor, Colin Runciman and Jason Reich,\nwho have kindly made their work available for others to use.  Please see\nhttps://mn416.github.io/reduceron-project/ (the original\nhttp://www.cs.york.ac.uk/fp/reduceron no longer works) for supporting\narticles, memos, and original distribution.\n\n\n## OK, WHAT'S THIS THEN?\n\nThe present is a fork of the original distribution with the aim of\nkeeping it running.  Originally there were more lofty\ngoals, but that's all abandonned.\n\nWhile Reduceron technically refers to the FPGA implementation, it is\nsupported by\n\n - Flite: the F-lite to Red translator.\n - A Red emulator in C\n - Red Lava: Reduceron is a Red Lava program, which generate Verilog\n - Support for Verilog simulation and synthesis for various FPGA boards\n\nAs much of the history as was available has been gathered and\nReduceron, Lava, and the Flite distribution have been merged into one\nrepository.\n\n\n## HOW DO I USE IT?\n\nThe was last tested with Glasgow Haskell Compiler, Version 8.4.4 on\nmacOS 10.14.3 and Linux, 64-bit.\n\nOptionally: just run make in the toplevel directory and a large\nregression run will start. The Verilog simulation part will take weeks to\nfinish.\n\nTo build:\n\n    make\n\nOr run a specific test suite:\n\n    make -C programs $X\n\nwhere $X is one of `regress-emu`, `regress-flite-sim`, `regress-flite-comp`, or\n`regress-red-verilog-sim`.\n\nNote: the code generated by the C backend for Flite (used in the\n`regress-flite-comp`) depends on GCC features, such as nested\nfunctions.  To build on macOS, install *real* gcc (say via Mac\nHomebrew) and invoke make as `make CC=gcc-7` (assuming you installed\nversion 7 of gcc).\n\nTo build a hardware version of a given test\n\n    cd fpga; make \u0026\u0026 flite -r ../programs/$P | ./Red -v\n\nwhere $P is one of the programs (.hs).  Next, build a Reduceron system\nfor an FPGA board, fx the BeMicroCV A9:\n\n    make -C Reduceron/BeMicroCV-A9\n\nUnfortunately programs can't currently be loaded dynamically but are\nbaked into the FPGA image.  It's a high priority goal to change that.\n\n## OPEN QUESTIONS, with answers from Matthew:\n\nQ1: Currently there doesn't seem an efficient way to handle toplevel\n    variable bindings (CAFs).  What did the York team have in mind there\n    or does it require an extension?  (Obviously one can treat them all\n    other functional arguments, but that would mean a lot of parameters\n    to pass around).\n\nA1: \"Some mechanism would be needed to construct graphs at a specified\nlocation on the heap at the beginning of program execution.  The\ninitial (unevaluated) graphs have constant size so can be linked to at\ncompile time.\"\n\n\nQ2: Why does Flite default to 0 for the MAXREGS parameter?  Eg, why is\n\n      redDefaults = CompileToRed 6 4 2 1 0\n\nA2: (Historical reasons it would appear).\n\n\nQ3: What happend to Memo 24?\n\nA3: \"I'd like to say it was our best kept secret, but in reality it\nprobably got trashed :)\"\n\n[![tip for next commit](http://prime4commit.com/projects/273.svg)](http://prime4commit.com/projects/273)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftommythorn%2Freduceron","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftommythorn%2Freduceron","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftommythorn%2Freduceron/lists"}