{"id":19958481,"url":"https://github.com/trabucayre/openfpgaloader","last_synced_at":"2025-05-14T02:04:55.699Z","repository":{"id":37827805,"uuid":"211133953","full_name":"trabucayre/openFPGALoader","owner":"trabucayre","description":"Universal utility for programming FPGA","archived":false,"fork":false,"pushed_at":"2025-05-10T05:07:43.000Z","size":7389,"stargazers_count":1319,"open_issues_count":92,"forks_count":289,"subscribers_count":38,"default_branch":"master","last_synced_at":"2025-05-10T06:18:26.701Z","etag":null,"topics":["arty","bitstream","cyclone","fpga","gowin","intel","lattice","trenz-gowin-littlebee","xilinx"],"latest_commit_sha":null,"homepage":"https://trabucayre.github.io/openFPGALoader/","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/trabucayre.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2019-09-26T16:27:32.000Z","updated_at":"2025-05-10T05:02:25.000Z","dependencies_parsed_at":"2023-10-03T10:23:18.662Z","dependency_job_id":"8520b5e8-74f3-4018-9e9e-3b68d9488aa1","html_url":"https://github.com/trabucayre/openFPGALoader","commit_stats":{"total_commits":1070,"total_committers":92,"mean_commits":"11.630434782608695","dds":"0.28785046728971964","last_synced_commit":"ccdcc49cb0b4fa623da5a762ba2ee0964c204bc6"},"previous_names":[],"tags_count":22,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trabucayre%2FopenFPGALoader","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trabucayre%2FopenFPGALoader/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trabucayre%2FopenFPGALoader/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trabucayre%2FopenFPGALoader/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/trabucayre","download_url":"https://codeload.github.com/trabucayre/openFPGALoader/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254052692,"owners_count":22006716,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["arty","bitstream","cyclone","fpga","gowin","intel","lattice","trenz-gowin-littlebee","xilinx"],"created_at":"2024-11-13T01:43:16.752Z","updated_at":"2025-05-14T02:04:55.680Z","avatar_url":"https://github.com/trabucayre.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# openFPGALoader\n\n\u003cp align=\"right\"\u003e\n  \u003ca title=\"Documentation\" href=\"https://trabucayre.github.io/openFPGALoader\"\u003e\u003cimg src=\"https://img.shields.io/website.svg?label=trabucayre.github.io%2FopenFPGALoader\u0026longCache=true\u0026style=flat-square\u0026url=http%3A%2F%2Ftrabucayre.github.io%2FopenFPGALoader%2Findex.html\u0026logo=GitHub\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"'Test' workflow Status\" href=\"https://github.com/trabucayre/openFPGALoader/actions/workflows/Test.yml\"\u003e\u003cimg alt=\"'Test' workflow Status\" src=\"https://img.shields.io/github/actions/workflow/status/trabucayre/openFPGALoader/Test.yml?branch=master\u0026longCache=true\u0026style=flat-square\u0026label=Test\u0026logo=github%20actions\u0026logoColor=fff\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"Releases\" href=\"https://github.com/trabucayre/openFPGALoader/releases\"\u003e\u003cimg src=\"https://img.shields.io/github/commits-since/trabucayre/openFPGALoader/latest.svg?longCache=true\u0026style=flat-square\u0026logo=git\u0026logoColor=fff\"\u003e\u003c/a\u003e\n\u003c/p\u003e\n\n\u003cp align=\"center\"\u003e\n  \u003cstrong\u003e\u003ca href=\"https://trabucayre.github.io/openFPGALoader/guide/first-steps.html\"\u003eFirst steps\u003c/a\u003e • \u003ca href=\"https://trabucayre.github.io/openFPGALoader/guide/install.html\"\u003eInstall\u003c/a\u003e • \u003ca href=\"https://trabucayre.github.io/openFPGALoader/guide/troubleshooting.html\"\u003eTroubleshooting\u003c/a\u003e\u003c/strong\u003e • \u003ca href=\"https://trabucayre.github.io/openFPGALoader/guide/advanced.html\"\u003eAdvanced usage\u003c/a\u003e\n\u003c/p\u003e\n\nUniversal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.\n\nNot sure if your hardware is supported? Check the hardware compatibility lists:\n\n * [FPGA compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/fpga.html)\n * [Board compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/board.html)\n * [Cable compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)\n\nAlso checkout the vendor-specific documentation:\n[Anlogic](https://trabucayre.github.io/openFPGALoader/vendors/anlogic.html),\n[Cologne Chip](https://trabucayre.github.io/openFPGALoader/vendors/colognechip.html),\n[Efinix](https://trabucayre.github.io/openFPGALoader/vendors/efinix.html),\n[Gowin](https://trabucayre.github.io/openFPGALoader/vendors/gowin.html),\n[Intel/Altera](https://trabucayre.github.io/openFPGALoader/vendors/intel.html),\n[Lattice](https://trabucayre.github.io/openFPGALoader/vendors/lattice.html),\n[Xilinx](https://trabucayre.github.io/openFPGALoader/vendors/xilinx.html).\n\nOpenFPGALoader has a dedicated channel: [#openFPGALoader at libera.chat](https://web.libera.chat/#openFPGALoader).\n\n## Quick Usage\n\n`arty` in the example below is one of the many FPGA board configurations listed [here](https://trabucayre.github.io/openFPGALoader/compatibility/board.html).\n\n```bash\nopenFPGALoader -b arty arty_bitstream.bit # Loading in SRAM\nopenFPGALoader -b arty -f arty_bitstream.bit # Writing in flash\n```\n\nYou can also specify a JTAG cable model (complete list [here](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)) instead of the board model:\n\n```bash\nopenFPGALoader -c cmsisdap fpga_bitstream.bit\n```\n\n## Usage\n\n```\nUsage: openFPGALoader [OPTION...] BIT_FILE\nopenFPGALoader -- a program to flash FPGA\n\n      --altsetting arg          DFU interface altsetting (only for DFU mode)\n      --bitstream arg           bitstream\n      --secondary-bitstream arg\n                                secondary bitstream (some Xilinx UltraScale\n                                boards)\n  -b, --board arg               board name, may be used instead of cable\n  -B, --bridge arg              disable spiOverJtag model detection by\n                                providing bitstream(intel/xilinx)\n  -c, --cable arg               jtag interface\n      --status-pin arg          JTAG mode / FTDI: GPIO pin number to use as a\n                                status indicator (active low)\n      --invert-read-edge        JTAG mode / FTDI: read on negative edge\n                                instead of positive\n      --vid arg                 probe Vendor ID\n      --pid arg                 probe Product ID\n      --cable-index arg         probe index (FTDI and cmsisDAP)\n      --busdev-num arg          select a probe by it bus and device number\n                                (bus_num:device_addr)\n      --ftdi-serial arg         FTDI chip serial number\n      --ftdi-channel arg        FTDI chip channel number (channels 0-3 map to\n                                A-D)\n  -d, --device arg              device to use (/dev/ttyUSBx)\n      --detect                  detect FPGA, add -f to show connected flash\n      --dfu                     DFU mode\n      --dump-flash              Dump flash mode\n      --bulk-erase              Bulk erase flash\n      --enable-quad             Enable quad mode for SPI Flash\n      --disable-quad            Disable quad mode for SPI Flash\n      --target-flash arg        for boards with multiple flash chips (some\n                                Xilinx UltraScale boards), select the target\n                                flash: primary (default), secondary or both\n      --external-flash          select ext flash for device with internal and\n                                external storage\n      --file-size arg           provides size in Byte to dump, must be used\n                                with dump-flash\n      --file-type arg           provides file type instead of let's deduced\n                                by using extension\n      --flash-sector arg        flash sector (Lattice and Altera MAX10 parts only)\n      --fpga-part arg           fpga model flavor + package\n      --freq arg                jtag frequency (Hz)\n  -f, --write-flash             write bitstream in flash (default: false)\n      --index-chain arg         device index in JTAG-chain\n      --misc-device arg         add JTAG non-FPGA devices \u003cidcode,irlen,name\u003e\n      --ip arg                  IP address (XVC and remote bitbang client)\n      --list-boards             list all supported boards\n      --list-cables             list all supported cables\n      --list-fpga               list all supported FPGA\n  -m, --write-sram              write bitstream in SRAM (default: true)\n  -o, --offset arg              Start address (in bytes) for read/write into\n                                non volatile memory (default: 0)\n      --pins arg                pin config TDI:TDO:TCK:TMS\n      --probe-firmware arg      firmware for JTAG probe (usbBlasterII)\n      --protect-flash arg       protect SPI flash area\n      --quiet                   Produce quiet output (no progress bar)\n  -r, --reset                   reset FPGA after operations\n      --scan-usb                scan USB to display connected probes\n      --skip-load-bridge        skip writing bridge to SRAM when in\n                                write-flash mode\n      --skip-reset              skip resetting the device when in write-flash\n                                mode\n      --spi                     SPI mode (only for FTDI in serial mode)\n      --unprotect-flash         Unprotect flash blocks\n  -v, --verbose                 Produce verbose output\n      --verbose-level arg       verbose level -1: quiet, 0: normal,\n                                1:verbose, 2:debug\n  -h, --help                    Give this help list\n      --verify                  Verify write operation (SPI Flash only)\n      --xvc                     Xilinx Virtual Cable Functions\n      --port arg                Xilinx Virtual Cable and remote bitbang Port\n                                (default 3721)\n      --mcufw arg               Microcontroller firmware\n      --conmcu                  Connect JTAG to MCU\n  -D, --read-dna                Read DNA (Xilinx FPGA only)\n  -X, --read-xadc               Read XADC (Xilinx FPGA only)\n      --read-register arg       Read Status Register(Xilinx FPGA only)\n  -V, --Version                 Print program version\n\nMandatory or optional arguments to long options are also mandatory or optional\nfor any corresponding short options.\n\nReport bugs to \u003cgwenhael.goavec-merou@trabucayre.com\u003e.\n```\n\nBy default **spiOverJtag** are search into `${CMAKE_INSTALL_FULL_DATAROOTDIR}`\n(*/usr/local/share/* by default). It's possible to change this behaviour by\nusing an environment variable:\n\n```bash\nexport OPENFPGALOADER_SOJ_DIR=/somewhere\nopenFPGALoader xxxx\n```\n\nor\n\n```\nOPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx\n```\n\n`OPENFPGALOADER_SOJ_DIR` must point to directory containing **spiOverJtag**\nbitstreams.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrabucayre%2Fopenfpgaloader","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftrabucayre%2Fopenfpgaloader","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrabucayre%2Fopenfpgaloader/lists"}