{"id":18392206,"url":"https://github.com/trcwm/fptool","last_synced_at":"2025-04-07T03:33:58.011Z","repository":{"id":149223882,"uuid":"58380165","full_name":"trcwm/fptool","owner":"trcwm","description":"Compiler for generating fixed-point logic using VHDL","archived":true,"fork":false,"pushed_at":"2024-06-20T12:22:51.000Z","size":238,"stargazers_count":9,"open_issues_count":1,"forks_count":0,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-03-02T00:34:46.024Z","etag":null,"topics":["arithmetic","fixed-point","hdl","signal-processing","vhdl"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/trcwm.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2016-05-09T13:50:22.000Z","updated_at":"2024-12-12T02:29:31.000Z","dependencies_parsed_at":"2024-11-06T02:03:22.633Z","dependency_job_id":"220f081b-d433-43b6-8ab3-2bc071f1699f","html_url":"https://github.com/trcwm/fptool","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trcwm%2Ffptool","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trcwm%2Ffptool/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trcwm%2Ffptool/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trcwm%2Ffptool/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/trcwm","download_url":"https://codeload.github.com/trcwm/fptool/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247589583,"owners_count":20963019,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["arithmetic","fixed-point","hdl","signal-processing","vhdl"],"created_at":"2024-11-06T01:54:39.579Z","updated_at":"2025-04-07T03:33:57.770Z","avatar_url":"https://github.com/trcwm.png","language":"C++","readme":"# FPTOOL README\n## A compiler for generating fixed-point VHDL code.\n### Niels A. Moseley\n\nThe fixed-point tool (FPTOOL) takes mathematical expressions and fixed-point input variable definitions, and transforms them into VHDL (or verilog in the future). The compiler takes care of the precision/width of each intermediate result to avoid overflows.\n\nIt is designed to be most useful for digital signal processing arithmetic running in a single clock domain.\n\nThe compiler can generate multipliers with Canonical Signed Digit (CSD) constants, leading to area-efficient implementations.\n\nAssumptions:\n\n- all variables are SIGNED.\n- all intermediate results are scaled to avoid overflow.\n- all shift operators are of the arithmetic type and don't drop bits. (SHIFT OPERATION UNSUPPORTED)\n- division is unsupported: multiply by 1/x.\n- you know what you're doing: optimizations are not done (for now).\n- Q(n,m) has 'm' factional bits and 'n' integer bits.\n- the number of bits in a Q(n,m) is n+m.\n- Q(1,7) has a range of [-1/128 .. 1/127], i.e. it can't represent 1.0 exactly.\n\nBuilt-in functions:\n\n- saturate(x,n,m) saturates variable 'x' to fit it into a Q(n,m) variable. (STILL UNSUPPORTED)\n- truncate(x,n,m) removes (or adds) bits to variable 'x' so it becomes Q(n,m).\n\nOperators:\n\n- regular arithmetic: '+' '-' '*'\n- line comment: '%'\n- division operator is accepted but code for it will no be generated.\n\nCurrent project state:\n\n- Lexer is working.\n- Parser can check the grammar (Except \u003c\u003c, \u003e\u003e, \u003c\u003c\u003c, \u003e\u003e\u003e and saturate) and build an abstract syntax tree.\n- VHDL code generator is working (except for division operator)\n- CSD expansion is working.\n- Don't use it for production unless you test the output thoroughly!!\n\n## Building\nLoad the project file (.pro) into [QtCreator](https://www.qt.io/ide/), configure the project for your compiler, then select Build-\u003eBuild All.\n\n## Command line options\n\n- \"-o VHDLFILENAME\" to generate VHDL source code.\n- \"-g DOTFILENAME\" to generate Graphviz/Dot formatted AST dump.\n- \"-L LOGFILE\" to write the output to a log file.\n- \"-V\" to enable verbose output.\n- \"-d\" to enable debug output.\n\n## Internal program flow\n* The input file is read by the lexer. It produces a list of tokens.\n* The parser analyses the tokens to check the syntax and collect data on variables/identifiers etc. It produces an abstract syntax tree (AST).\n* The AST is transformed to a single-static-assigment (SSA) form, i.e. a list of simple assignments.\n* Several micro passes (transformations) are performed on the SSA to remove the more complex commands and/or operands, such as multiplcations by a canonical signed digit constant.\n* Finally, the VHDL code generate takes the final SSA list and transforms it into VHDL statements and associated documentation.\n\nLicense: GPL v2.\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrcwm%2Ffptool","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftrcwm%2Ffptool","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrcwm%2Ffptool/lists"}