{"id":15047742,"url":"https://github.com/trisycl/trisycl","last_synced_at":"2025-05-15T14:04:59.343Z","repository":{"id":16197161,"uuid":"18943874","full_name":"triSYCL/triSYCL","owner":"triSYCL","description":" Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group","archived":false,"fork":false,"pushed_at":"2024-11-02T01:11:38.000Z","size":400897,"stargazers_count":443,"open_issues_count":117,"forks_count":98,"subscribers_count":45,"default_branch":"master","last_synced_at":"2025-05-15T14:04:58.621Z","etag":null,"topics":["cpp","cpp20","fpga","gpu-computing","heterogeneous-parallel-programming","opencl","spir","sycl","trisycl"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/triSYCL.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.TXT","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2014-04-19T15:19:51.000Z","updated_at":"2025-05-15T13:45:08.000Z","dependencies_parsed_at":"2023-01-11T20:24:38.778Z","dependency_job_id":"fb9bf854-d59c-463c-a5b8-33a453e3039c","html_url":"https://github.com/triSYCL/triSYCL","commit_stats":{"total_commits":1964,"total_committers":29,"mean_commits":67.72413793103448,"dds":"0.22963340122199594","last_synced_commit":"8eaec07bd782d2cc1994ab4baeb80abdf747fff3"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/triSYCL%2FtriSYCL","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/triSYCL%2FtriSYCL/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/triSYCL%2FtriSYCL/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/triSYCL%2FtriSYCL/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/triSYCL","download_url":"https://codeload.github.com/triSYCL/triSYCL/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254355334,"owners_count":22057354,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpp","cpp20","fpga","gpu-computing","heterogeneous-parallel-programming","opencl","spir","sycl","trisycl"],"created_at":"2024-09-24T21:04:08.644Z","updated_at":"2025-05-15T14:04:59.323Z","avatar_url":"https://github.com/triSYCL.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"triSYCL\n+++++++\n\n..\n  Not supported by GitHub :-(\n  include:: doc/common-includes.rst\n\n.. section-numbering::\n\n.. highlight:: C++\n\n..\n  Add a badge with the build status of the CI\n  Cf https://docs.github.com/en/actions/managing-workflow-runs/adding-a-workflow-status-badge\n.. image:: https://github.com/triSYCL/triSYCL/actions/workflows/cmake.yml/badge.svg\n    :target: https://github.com/triSYCL/triSYCL/actions\n\nIntroduction\n------------\n\ntriSYCL_ is a research project to experiment with the specification of\nthe SYCL_ standard and to give feedback to the Khronos_ Group\nSYCL_committee and also to the ISO `C++`_ committee.\n\nMore recently, this project has been used to experiment with high-level C++\nprogramming for AMD_ AIE CGRA inspired by some SYCL concepts, as explained in\n`ACAP++ \u0026 AIE++: C++ extensions for AMD Versal AIE CGRA architecture`_.\n\nBecause of lack of resources **this SYCL implementation is very\nincomplete and should not be used by a normal end-user.** Fortunately\nthere are now many other implementations of SYCL_ available, including\nsome strong implementations like `DPC++`_ or hipSYCL_\nthat can be used on various targets.\n\nThis implementation is mainly based on C++23 features backed with\nOpenMP_ or TBB_ for parallel execution on the CPU, with\n`Boost.Compute`_ for the non single-source OpenCL_ interoperability\nlayer and with an experimental LLVM_/Clang_ version for the device\ncompiler (from 2017-2018 which is now obsolete) providing full\nsingle-source SYCL_ experience, typically targeting a SPIR_\ndevice. Since in SYCL_ there is a host fall-back, this CPU\nimplementation can be seen as an implementation of this fall-back too.\n\nSince around 2018 Intel has put a lot of effort in their own oneAPI\n`DPC++`_ SYCL_ project to up-stream SYCL_ into LLVM_/Clang_, there is\nanother project about merging the oneAPI `DPC++`_ SYCL_ implementation\nwith triSYCL_ at https://github.com/triSYCL/sycl to give a greater\nuser experience for AMD_ FPGA instead of using our obsolete\nexperimental clunky device compiler. But this is still very\nexperimental because the AMD_ tool-chain is based on old\nincompatible versions of LLVM_/Clang_ and nothing of these is\nsupported by the AMD_ product teams.\n\ntriSYCL_ has been used to experiment and provide feedback for SYCL_\n1.2, 1.2.1, 2.2, 2020 and even the OpenCL_ C++ 1.0 kernel language\nfrom OpenCL_ 2.2.\n\nThis is provided as is, without any warranty, with the same license as\nLLVM_/Clang_.\n\nTechnical lead: Ronan at keryell point FR. Developments started first\nat AMD_, then was mainly funded by Xilinx_ and now again by AMD_ since\nXilinx_ has been acquired by AMD_ in 2022.\n\nIt is possible to have a paid internship around triSYCL, if you have\nsome skills related to this project. Contact the technical lead about\nthis. AMD_ is also hiring in this area... :-)\n\n\nSYCL\n----\n\nSYCL_ is a single-source modern C++-based DSEL_ (Domain Specific\nEmbedded Language) and open standard from Khronos_ aimed at\nfacilitating the programming of heterogeneous accelerators by\nleveraging existing concepts inspired by OpenCL_, CUDA_, `C++AMP`_, OpenMP_...\n\nA typical kernel with its launch looks like this pure modern C++ code::\n\n  queue {}.submit([\u0026](handler \u0026h) {\n      auto accA = bufA.get_access\u003caccess::mode::read\u003e(h);\n      auto accB = bufB.get_access\u003caccess::mode::write\u003e(h);\n      h.parallel_for\u003cclass myKernel\u003e(myRange, [=](item i) {\n          accA[i] = accB[i] + 1;\n      });\n  });\n\nLook for example at\nhttps://github.com/triSYCL/triSYCL/blob/master/tests/examples/demo_parallel_matrix_add.cpp\nfor a complete example.\n\nSYCL_ is developed inside the Khronos_ SYCL_ committee and thus, for\nmore information on SYCL_, look at https://www.khronos.org/sycl\n\nNote that even if the concepts behind SYCL_ are inspired by OpenCL_\nconcepts, the SYCL_ programming model is a very general asynchronous\ntask graph model for heterogeneous computing targeting various\nframeworks and API and has *no* relation with OpenCL_ itself, except\nwhen using the OpenCL_ API interoperability mode, like any other\ntarget.\n\nFor the SYCL_ ecosystem, look at https://sycl.tech\n\n\nACAP++ \u0026 AIE++: C++ extensions for AMD Versal AIE CGRA architecture\n-------------------------------------------------------------------\n\nMost of our current efforts are focused on extensions, such as targeting AMD_\nFPGA and Versal ACAP AIE CGRA, providing a way to program CPU, GPU, FPGA and\nCGRA at the same time in a single-source C++ program.\n\nThis project is a work-in-progress and currently we target partially only the\nfirst generation of devices, AIE/AIE1, while current models of AMD_ RyzenAI such\nas the Ryzen 9 7940HS has an AIE-ML/AIE2 as the XDNA/NPU/IPU.\n\n- The first generation programming model, `ACAP++` was based on C++17/C++20\n  constructs.\n\n  See\n  https://github.com/triSYCL/sycl/blob/sycl/unified/master/sycl/test/acap/test_aie_mandelbrot.cpp\n  and around, `\u003ctests/acap\u003e`_ and other directories starting with `acap` for\n  some code samples running in pure C++ library CPU emulation with this project.\n\n  Look at `\u003cdoc/acap.rst\u003e`_ to know more about how to install/use the ACAP++\n  environment.\n\n  The runtime for CPU emulation and AIE device is found in\n  `\u003cinclude/triSYCL/vendor/Xilinx\u003e`_ which requires also a special compiler\n  provided by https://github.com/triSYCL/sycl to run on VCK190 boards.\n\n- The second generation programming model, `AIE++` is based on C++23/C++26\n  constructs, allowing an even terser syntax.\n\n  See around\n  `\u003chttps://github.com/triSYCL/sycl/blob/sycl/unified/master/sycl/test/aie/mandelbrot.cpp\u003e`_\n  for some examples.\n\n  The runtime for CPU emulation and AIE device support is found in\n  `\u003cinclude/aie\u003e`_ and the compiler for device support is\n  https://github.com/triSYCL/sycl\n\nOther open-source projects related to AIE which are interesting to program AIE:\n\n- https://riallto.ai\n\n- https://github.com/Xilinx/mlir-aie\n\n- https://github.com/Xilinx/mlir-air\n\n- https://github.com/nod-ai/iree-amd-aie\n\nSome documentation about AMD AIE CGRA:\n\n- AIE aka AIE1\n\n  - Versal Adaptive SoC AI Engine Architecture Manual\n    https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Overview\n\n  - Versal Adaptive SoC Technical Reference Manual\n    https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Introduction\n\n  - AIE/AIE1 C++ API\n    https://www.xilinx.com/htmldocs/xilinx2024_1/aiengine_api/aie_api/doc\n\n- AIE-ML aka AIE2\n\n  - AIE2/AIE-ML architecture\n    https://docs.xilinx.com/r/en-US/am020-versal-aie-ml/Overview\n\n  - AIE2/AIE-ML C++ API\n    https://www.xilinx.com/htmldocs/xilinx2024_1/aiengine_ml_intrinsics/intrinsics\n\n\nDocumentation\n-------------\n\nSome reasons to use SYCL\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nPlease see `about SYCL \u003cdoc/about-sycl.rst\u003e`_ to have some context, a\nlist of presentations, some related projects.\n\n\nInstallation \u0026 testing\n~~~~~~~~~~~~~~~~~~~~~~\n\nSYCL_ is a template library, so no real installation is required.\n\nThere are some examples you can build however.\n\nSee `Testing \u003cdoc/testing.rst\u003e`_.\n\n\nArchitecture of triSYCL runtime and compiler\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n`Architecture of triSYCL runtime and compiler \u003cdoc/architecture.rst\u003e`_\ndescribes the code base with some high-level diagrams but also how it\nwas possible to compile and use the obsolete device compiler on some AMD_\nFPGA for example. Now look at https://github.com/triSYCL/sycl instead.\n\n\nCMake infrastructure\n~~~~~~~~~~~~~~~~~~~~\n\nSome details about CMake configuration and organization can be found\nin `CMake \u003cdoc/cmake.rst\u003e`_.\n\n\nPre-processor macros used in triSYCL\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nYes, there are some macros used in triSYCL! Look at `Pre-processor\nmacros used in triSYCL \u003cdoc/macros.rst\u003e`_ to discover some of them.\n\n\nEnvironment variables used in triSYCL\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSee `Environment variables with triSYCL \u003cdoc/environment.rst\u003e`_.\n\n\nPossible futures\n~~~~~~~~~~~~~~~~\n\nSee `Possible futures \u003cdoc/possible-futures.rst\u003e`_.\n\n\ntriSYCL code documentation\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe documentation of the triSYCL_ implementation itself can be found\nin https://trisycl.github.io/triSYCL/Doxygen/triSYCL/html and\nhttps://trisycl.github.io/triSYCL/Doxygen/triSYCL/triSYCL-implementation-refman.pdf\n\n\nNews\n----\n\n- 2023/06/09: merge the 5-year old branch experimenting with ACAP++\n  SYCL CPU model extensions for AMD_ Versal ACAP AIE1 CGRA like the\n  XCVC1902 used in VCK190 or VCK5000 boards.\n\n- 2018/03/12: the long-going device compiler branch has been merged in\n  to provide experimental support for SPIR-df friendly devices, such\n  as PoCL_ or Xilinx_ FPGA. This is only for the brave for now.\n\n- 2018/02/01: there is now some documentation about the architecture of\n  triSYCL on GPU and accelerators with its device compiler based on\n  Clang_/LLVM_ in `\u003cdoc/architecture.rst\u003e`_. While this is wildly\n  experimental, there is a growing interest around it and it is\n  always useful to get started as a contributor.\n\n- 2018/01/05: there are some internship openings at Xilinx_ to work on\n  triSYCL for FPGA\n  https://xilinx.referrals.selectminds.com/jobs/compiler-engineer-intern-on-sycl-for-fpga-4685\n  and more generally Xilinx_ is hiring in compilation, runtime, C++,\n  SYCL_, OpenCL_, machine-learning...\n\n- 2017/12/06: the brand-new SYCL 1.2.1 specification is out and\n  triSYCL starts moving to it\n\n- 2017/11/17: the presentations and videos from `SC17\n  \u003chttps://sc17.supercomputing.org\u003e`_ on SYCL and triSYCL are now\n  online https://www.khronos.org/news/events/supercomputing-2017\n\n- 2017/09/19: there is a prototype of device compiler based on\n  Clang_/LLVM_ generating SPIR 2.0 \"de facto\" (SPIR-df) and working at least\n  with PoCL_ and Xilinx_ SDx `xocc` for FPGA.\n\n- 2017/03/03: triSYCL can use CMake \u0026 ``ctest`` and works on Windows 10 with\n  Visual Studio 2017. It works also with Ubuntu WSL on Windows. :-)\n  `More info \u003cdoc/cmake.rst\u003e`_\n\n- 2017/01/12: Add test case using the Xilinx_ compiler for FPGA\n\n- 2016/11/18: If you missed the free SYCL_ T-shirt on the Khronos booth\n  during SC16_, you can always buy some on\n  https://teespring.com/khronos-hpc (lady's sizes available, so no\n  excuse! :-) )\n\n- 2016/08/12: OpenCL_ kernels can be run with OpenCL_ kernel\n  interoperability mode now.\n\n- 2016/04/18: SYCL_ 2.2 provisional specification is out. This version\n  implement SYCL_ 2.2 pipes and reservations plus the blocking pipe\n  extension from Xilinx_.\n\n\n..\n  Actually include:: doc/common-includes.rst does not work in GitHub\n  :-( https://github.com/github/markup/issues/172\n\n  So manual inline of the following everywhere... :-(\n\n.. Some useful link definitions:\n\n.. _AMD: https://www.amd.com\n\n.. _Bolt: https://github.com/HSA-Libraries/Bolt\n\n.. _Boost.Compute: https://github.com/boostorg/compute\n\n.. _C++: https://www.open-std.org/jtc1/sc22/wg21/\n\n.. _committee: https://isocpp.org/std/the-committee\n\n.. _C++AMP: https://msdn.microsoft.com/en-us/library/hh265137.aspx\n\n.. _Clang: https://clang.llvm.org/\n\n.. _CLHPP: https://github.com/KhronosGroup/OpenCL-CLHPP\n\n.. _Codeplay: https://www.codeplay.com\n\n.. _ComputeCpp: https://www.codeplay.com/products/computesuite/computecpp\n\n.. _CUDA: https://developer.nvidia.com/cuda-zone\n\n.. _DirectX: https://en.wikipedia.org/wiki/DirectX\n\n.. _DPC++: https://github.com/intel/llvm/tree/sycl\n\n.. _DSEL: https://en.wikipedia.org/wiki/Domain-specific_language\n\n.. _Eigen: https://eigen.tuxfamily.org\n\n.. _Fortran: https://en.wikipedia.org/wiki/Fortran\n\n.. _GCC: https://gcc.gnu.org/\n\n.. _GOOPAX: https://www.goopax.com/\n\n.. _HCC: https://github.com/RadeonOpenCompute/hcc\n\n.. _HIP: https://github.com/ROCm-Developer-Tools/HIP\n\n.. _hipSYCL: https://github.com/illuhad/hipSYCL\n\n.. _HSA: https://www.hsafoundation.com/\n\n.. _Khronos: https://www.khronos.org/\n\n.. _LLVM: https://llvm.org/\n\n.. _Metal: https://developer.apple.com/library/ios/documentation/Metal/Reference/MetalShadingLanguageGuide\n\n.. _MPI: https://en.wikipedia.org/wiki/Message_Passing_Interface\n\n.. _OpenACC: https://www.openacc-standard.org/\n\n.. _OpenAMP: https://www.multicore-association.org/workgroup/oamp.php\n\n.. _OpenCL: https://www.khronos.org/opencl/\n\n.. _OpenGL: https://www.khronos.org/opengl/\n\n.. _OpenHMPP: https://en.wikipedia.org/wiki/OpenHMPP\n\n.. _OpenMP: https://openmp.org/\n\n.. _PACXX: https://pacxx.github.io/page/\n\n.. _PoCL: https://portablecl.org/\n\n.. _SYCL Parallel STL: https://github.com/KhronosGroup/SyclParallelSTL\n\n.. _RenderScript: https://en.wikipedia.org/wiki/Renderscript\n\n.. _SC16: https://sc16.supercomputing.org\n\n.. _SG14: https://groups.google.com/a/isocpp.org/forum/?fromgroups=#!forum/sg14\n\n.. _SPIR: https://www.khronos.org/spir\n\n.. _SPIR-V: https://www.khronos.org/spir\n\n.. _SYCL: https://www.khronos.org/sycl\n\n.. _TensorFlow: https://www.tensorflow.org\n\n.. _TBB: https://www.threadingbuildingblocks.org/\n\n.. _Thrust: https://thrust.github.io/\n\n.. _triSYCL: https://github.com/triSYCL/triSYCL\n\n.. _VexCL: https://ddemidov.github.io/vexcl/\n\n.. _ViennaCL: https://viennacl.sourceforge.net/\n\n.. _Vulkan: https://www.khronos.org/vulkan/\n\n.. _Xilinx: https://www.xilinx.com\n\n..\n    # Some Emacs stuff:\n    ### Local Variables:\n    ### mode: rst\n    ### minor-mode: flyspell\n    ### ispell-local-dictionary: \"american\"\n    ### End:\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrisycl%2Ftrisycl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftrisycl%2Ftrisycl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrisycl%2Ftrisycl/lists"}