{"id":13649148,"url":"https://github.com/trivialmips/nontrivial-mips","last_synced_at":"2025-04-22T12:33:53.123Z","repository":{"id":41456410,"uuid":"171665435","full_name":"trivialmips/nontrivial-mips","owner":"trivialmips","description":"NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.","archived":false,"fork":false,"pushed_at":"2020-07-07T04:44:00.000Z","size":21347,"stargazers_count":559,"open_issues_count":0,"forks_count":95,"subscribers_count":27,"default_branch":"master","last_synced_at":"2024-08-03T01:39:32.221Z","etag":null,"topics":["cpu","fpga","fpga-soc","fpga-soc-linux","mips","systemverilog","xilinx"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/trivialmips.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-02-20T12:02:17.000Z","updated_at":"2024-07-25T07:05:54.000Z","dependencies_parsed_at":"2022-08-10T02:27:14.369Z","dependency_job_id":null,"html_url":"https://github.com/trivialmips/nontrivial-mips","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trivialmips%2Fnontrivial-mips","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trivialmips%2Fnontrivial-mips/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trivialmips%2Fnontrivial-mips/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/trivialmips%2Fnontrivial-mips/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/trivialmips","download_url":"https://codeload.github.com/trivialmips/nontrivial-mips/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223896472,"owners_count":17221441,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","fpga","fpga-soc","fpga-soc-linux","mips","systemverilog","xilinx"],"created_at":"2024-08-02T01:04:48.384Z","updated_at":"2024-11-09T23:31:05.278Z","avatar_url":"https://github.com/trivialmips.png","language":"SystemVerilog","funding_links":[],"categories":["SystemVerilog"],"sub_categories":[],"readme":"# NonTrivialMIPS\n\nNonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and CP1 (FPU), CP2 (AES accelerator) support, and it is capable of booting fully-functional Linux.\n\n## Authors\n\nSee `AUTHORS` for information about the authors of this project.\n\n## Directory Structure\n\n* `loongson`: files from Loongson, some are adapted\n  * `cpu_gs232`: RTL code of GS232 CPU (__not included for copyright reason__), packaged as Vivado IP\n  * `soc_axi_func`: Vivado project, RTL code and testbench of functional test (using NonTrivialMIPS CPU)\n  * `soc_axi_perf`: Vivado project, RTL code and testbench of performance test (using NonTrivialMIPS CPU)\n  * `soc_run_os`: Vivado project and RTL code of a whole SoC (using GS232 CPU, upgraded to 2018.3)\n  * `soft`: RAM initialization files used by the projects above\n* `src`: RTL code of NonTrivialMIPS CPU\n* `vivado`: Vivado project and block design of NSCSCC SoC\n* `testbench`: Testbenches of NonTrivialMIPS CPU / NSCSCC Soc\n* `report`: Design reports (LaTeX srouce code and rendered PDF)\n\n*Remark*: `out-of-order` branch contains a toy dual-issue out-of-order processor.\n\n## Build Project\n\n### Update submodules\n\nWe use git submodules to manage external code. Run `git submodule update --init` after cloning this project to ensure everything is up-to-date.\n\n### Compiling options\n\nNonTrivialMIPS CPU has some compiling flags that can control the features that will be enabled and parameters (such as cache size and associativity) that will be used. See `src/compile_options.svh` for details.\n\nNote that inappropriate changes made to these flags may lead to strange or WRONG behaviors of the CPU.\n\n### Generate bitstream\n\nYou can generate bitstreams that can be programmed to FPGA by following commands:\n\n```bash\n# for soc project\n/path/to/vivado -mode tcl -source scripts/build_soc.tcl vivado/TrivialMIPS.xpr\n# for loongson functional test\n/path/to/vivado -mode tcl -source scripts/generate_bitstream.tcl loongson/soc_axi_func/run_vivado/mycpu_prj1/mycpu.xpr\n# for loongson performance test\n/path/to/vivado -mode tcl -source scripts/generate_bitstream.tcl loongson/soc_axi_perf/run_vivado/mycpu_prj1/mycpu.xpr\n```\n\nVivado 2018.3 is required.\n\n## License\n\nAll source code under `src/` is released under the MIT License with the following exceptions:\n\n* `src/asic/aes/` is licensed under BSD-2-Clause License (source code from [GitHub](https://github.com/secworks/aes/))\n* `src/utils/fifo_v3.sv` is licesed under [The Solderpad Hardware Licence](https://solderpad.org/licenses/) (source code from [GitHub](https://github.com/pulp-platform/ariane))\n\nOther directories might contain source code or materials that are proprietary or subject to open source licenses and kept in this repository as-is.\nShould you use these contents, you are aware that you will bear any corresponding legal responsibility or consequences.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrivialmips%2Fnontrivial-mips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftrivialmips%2Fnontrivial-mips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftrivialmips%2Fnontrivial-mips/lists"}