{"id":26783280,"url":"https://github.com/truong92cdv/uart_fpga_esp32","last_synced_at":"2026-05-14T22:44:18.564Z","repository":{"id":277652907,"uuid":"933110516","full_name":"truong92cdv/UART_fpga_esp32","owner":"truong92cdv","description":"FPGA interface with ESP32 (or ESP8266) via UART protocol, connect to Thingsboard","archived":false,"fork":false,"pushed_at":"2025-02-18T17:36:08.000Z","size":1263,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-29T09:19:07.627Z","etag":null,"topics":["esp32","esp8266","fpga","thingsboard","uart","verilog","zuboard"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/truong92cdv.png","metadata":{},"created_at":"2025-02-15T06:56:44.000Z","updated_at":"2025-02-18T17:44:15.000Z","dependencies_parsed_at":null,"dependency_job_id":"bf4448c8-129f-45ab-9d64-659db9c1c572","html_url":"https://github.com/truong92cdv/UART_fpga_esp32","commit_stats":null,"previous_names":["truong92cdv/uart_fpga_esp32"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/truong92cdv/UART_fpga_esp32","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/truong92cdv%2FUART_fpga_esp32","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/truong92cdv%2FUART_fpga_esp32/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/truong92cdv%2FUART_fpga_esp32/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/truong92cdv%2FUART_fpga_esp32/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/truong92cdv","download_url":"https://codeload.github.com/truong92cdv/UART_fpga_esp32/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/truong92cdv%2FUART_fpga_esp32/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":281433289,"owners_count":26500408,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-28T02:00:06.022Z","response_time":60,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["esp32","esp8266","fpga","thingsboard","uart","verilog","zuboard"],"created_at":"2025-03-29T09:19:09.554Z","updated_at":"2025-10-28T11:47:25.062Z","avatar_url":"https://github.com/truong92cdv.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftruong92cdv%2Fuart_fpga_esp32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftruong92cdv%2Fuart_fpga_esp32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftruong92cdv%2Fuart_fpga_esp32/lists"}