{"id":26737104,"url":"https://github.com/tymonx/logic","last_synced_at":"2025-04-14T13:33:02.244Z","repository":{"id":48136364,"uuid":"108771045","full_name":"tymonx/logic","owner":"tymonx","description":"CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.","archived":false,"fork":false,"pushed_at":"2019-11-25T16:24:21.000Z","size":840,"stargazers_count":276,"open_issues_count":0,"forks_count":60,"subscribers_count":31,"default_branch":"master","last_synced_at":"2025-03-28T02:42:54.158Z","etag":null,"topics":["asic","cmake","cpp","fpga","hdl","modelsim","quartus","rtl","systemc","systemverilog","testing-rtl","unit-tests","uvm","verification","verilator","verilog","vivado","xilinx"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/tymonx.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2017-10-29T21:01:42.000Z","updated_at":"2025-03-02T07:07:22.000Z","dependencies_parsed_at":"2022-08-12T19:31:14.912Z","dependency_job_id":null,"html_url":"https://github.com/tymonx/logic","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tymonx%2Flogic","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tymonx%2Flogic/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tymonx%2Flogic/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tymonx%2Flogic/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/tymonx","download_url":"https://codeload.github.com/tymonx/logic/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248888783,"owners_count":21178104,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","cmake","cpp","fpga","hdl","modelsim","quartus","rtl","systemc","systemverilog","testing-rtl","unit-tests","uvm","verification","verilator","verilog","vivado","xilinx"],"created_at":"2025-03-28T02:37:39.989Z","updated_at":"2025-04-14T13:33:02.205Z","avatar_url":"https://github.com/tymonx.png","language":"SystemVerilog","readme":"Logic\n=====\n\n[![Language](https://img.shields.io/badge/language-C++-blue.svg?style=flat)](https://isocpp.org/)\n[![Standard](https://img.shields.io/badge/c%2B%2B-11/14/17-blue.svg?style=flat)](https://en.wikipedia.org/wiki/C%2B%2B#Standardization)\n[![Language](https://img.shields.io/badge/language-SystemVerilog-blue.svg?style=flat)](http://accellera.org/downloads/ieee)\n[![License Apache-2.0](https://img.shields.io/badge/license-Apache--2.0-blue.svg?style=flat)](https://choosealicense.com/licenses/apache-2.0/)\n[![Build Status](https://travis-ci.org/tymonx/logic.svg?branch=master)](https://travis-ci.org/tymonx/logic)\n[![Join the chat at https://gitter.im/tymonx/logic](https://badges.gitter.im/tymonx/logic.svg)](https://gitter.im/tymonx/logic?utm_source=badge\u0026utm_medium=badge\u0026utm_campaign=pr-badge\u0026utm_content=badge)\n\nCMake, SystemVerilog and SystemC utilities for creating, building and testing\nRTL projects for FPGAs and ASICs.\n\nIncludes:\n\n  * CMake utilities for rapid building and testing RTL projects\n  * SystemVerilog modules for creating high quality RTL projects\n  * Modern C++ framework for UVM with SystemC for creating high quality and\n    performance efficient tests for RTL projects\n\nBenefits\n--------\n\n  * Quick setup\n  * Cross platform, cross IDE\n  * No need to create separate scripts for simulation and synthesis\n  * No need to create separate scripts for different tools\n    (Intel Quartus, Xilinx Vivado, Verilator, ModelSim, ...)\n  * Supports incremental compilation, run slow vendor IP core regeneration and\n    different simulation and synthesis tools only if input source file changes\n  * Supports parallel compilation, run slow vendor IP core regeneration and\n    different simulation and synthesis tools in parallel\n  * Maintain the same file consistency between simulation and synthesis\n    for different tools\n  * Share the same HDL source code base and IP cores for various FPGA projects\n  * Integration with Continuous Integration (CI) and Continuous Deployment (CD)\n    like Jenkins, Hudson, GitLab, etc.\n  * Run RTL unit tests under ctest: pass/fail, time execution, timeout,\n    parallel execution, tests selection\n  * Run the same unit tests with different parameters\n  * Easy to integrate with other projects as git submodule\n  * Custom UVM printers: JSON\n  * Modern HDL testing library written in C++11 using UVM-SystemC\n  * Support for Clang 3.5 and later\n  * Support for GCC 4.9 and later\n\nDocumentation\n-------------\n\n  * [Wiki](https://github.com/tymonx/logic/wiki) - Main documentation\n  * [Environment setup for Linux](doc/environment-setup-linux.md)\n\nExamples\n--------\n\nFPGA projects that use **Logic** utilities for creating, building and testing:\n\n  * [Virtio](https://github.com/tymonx/virtio) - Virtio implementation\n\nRequirements\n------------\n\nThese 3rd party tools and libraries are required. They must be installed to\nbuild logic library:\n\n  * [CMake](https://cmake.org/) - build, test and package project\n  * [SystemC 2.3.2](http://accellera.org/downloads/standards/systemc) - SystemC C++ library\n  * [UVM-SystemC 1.0](http://www.eda.org/activities/working-groups/systemc-verification) - UVM for SystemC\n  * [SystemC Verification 2.0.1](http://accellera.org/downloads/standards/systemc) - SystemC data randomization\n\nThese 3rd party tools and libraries are optional. They must be installed to\nbuild and run tests:\n\n  * [Verilator](https://www.veripool.org/wiki/verilator/) - simulator, lint and coverage tool\n  * [GoogleTest](https://github.com/google/googletest) - C++ unit test framework\n  * [SVUnit](http://agilesoc.com/open-source-projects/svunit/) - SystemVerilog unit test framework\n\nThese 3rd party tools and libraries are optional:\n\n  * [Intel FPGA Quartus](https://www.altera.com/downloads/download-center.html) - synthesis tool for Intel FPGAs\n  * [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html) - synthesis tools for Xilinx FPGAs\n  * [Open Verification Library](http://accellera.org/activities/working-groups/ovl) - library of assertion checkers\n  * [Natural Docs](http://www.naturaldocs.org/) - code documentation generator\n  * [GTKWave](http://gtkwave.sourceforge.net/) - waveform viewer\n  * [WaveDrom](http://wavedrom.com/) - digital timing diagram\n\nWorkspace\n---------\n\n  * README.md       - this read me file in MarkDown format\n  * LICENSE         - license file\n  * CMakeLists.txt  - CMake root script for building and testing project\n  * doc             - configuration files for code documentation generator\n  * rtl             - RTL source files\n  * src             - C++ source files\n  * include         - C++ include headers\n  * tests           - unit tests and verification tests in SystemC using\n                      Google Test or UVM and SystemVerilog using SVUnit\n  * cmake           - additional CMake scripts for building project\n  * scripts         - additional scripts in TCL or Python for building project\n\nBuild\n-----\n\nClone project repository:\n\n    git clone git@github.com:tymonx/logic.git\n\nChange current location to project directory:\n\n    cd logic\n\nCreate build directory:\n\n    mkdir build\n\nChange current location to build directory:\n\n    cd build\n\nCreate build scripts using CMake:\n\n    cmake ..\n\nBuild project using CMake (generic):\n\n    cmake --build . --target all\n\nOr build project using make:\n\n    make -j`nproc`\n\nIt is much faster to recompile project using Ninja rather than Unix makefiles:\n\n    cmake -G Ninja ..\n    cmake --build . --target all\n\nDocumentation\n-------------\n\nTo build documentation:\n\n    cmake --build . target doc\n\nBuilt HTML documentation can be found in:\n\n    doc/html\n\nTo view HTML documentation, open it using web browser:\n\n    \u003cWEB_BROWSER\u003e doc/html/index.html\n\nTests\n-----\n\nRun all unit tests:\n\n    ctest\n\nRun only unit tests for AXI4-Stream:\n\n    ctest -R axi4_stream\n\nWaveforms from unit tests run under ModelSim are stored in:\n\n    modelsim/unit_tests/\u003cunit_test_name\u003e\n\nWaveforms from unit tests run under Verilator are stored in:\n\n    verilator/unit_tests/\u003cunit_test_name\u003e\n\nAll unit tests logs are stored in:\n\n    Testing/Temporary/LastTest.log\n\nVerilator Coverage\n------------------\n\nRun Verilator coverage after running all tests:\n\n    cmake --build . --target verilator-coverage\n\nVerilator analysis\n------------------\n\nEnable Verilator analysis:\n\n    add_hdl_source(\u003chdl-module-filename\u003e\n        ANALYSIS\n            TRUE\n    )\n\nRun Verilator analysis for `\u003chdl-module-name\u003e`:\n\n    make verilator-analysis-\u003chdl-module-name\u003e\n\nRun Verilator analysis for all HDL modules:\n\n    make verilator-analysis-all\n\nCreating Intel FPGA Quartus project\n-----------------------------------\n\nUse `add_quartus_project()` function to create Quartus project:\n\n    add_quartus_project(\u003ctop_level_entity\u003e)\n\nQuartus project will be created under:\n\n    quartus/\u003ctop_level_entity\u003e\n\nRTL analysis and elaboration in `Intel FPGA Quartus` for top level entity:\n\n    cmake --build . --target quartus-analysis-\u003ctop_level_entity\u003e\n\nRTL compilation in `Intel FPGA Quartus` for top level entity:\n\n    cmake --build . --target quartus-compile-\u003ctop_level_entity\u003e\n\nRTL analysis and elaboration in `Intel FPGA Quartus` for all top level\nentities:\n\n    cmake --build . --target quartus-analysis-all\n\nRTL compilation in `Intel FPGA Quartus` for all top level entities:\n\n    cmake --build . --target quartus-compile-all\n\nCreating Xilinx Vivado project\n------------------------------\n\nUse `add_vivado_project()` function to create Vivado project:\n\n    add_vivado_project(\u003ctop_level_entity\u003e)\n\nVivado project will be created under:\n\n    vivado/\u003ctop_level_entity\u003e\n\nRTL analysis and elaboration in `Xilinx Vivado` for top level entity:\n\n    cmake --build . --target vivado-analysis-\u003ctop_level_entity\u003e\n\nUsing with other CMake projects\n-------------------------------\n\nChange current location to another RTL project root directory:\n\n    cd \u003crtl_project_root_directory\u003e\n\nClone and add logic repository to RTL project as git submodule:\n\n    git submodule add git@github.com:tymonx/logic.git\n\nAdd these lines to CMakeLists.txt root file:\n\n    set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH}\n        ${CMAKE_CURRENT_LIST_DIR}/logic/cmake\n    )\n\n    include(AddLogic)\n\n    enable_testing()\n\n    add_subdirectory(logic)\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftymonx%2Flogic","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ftymonx%2Flogic","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ftymonx%2Flogic/lists"}