{"id":26930413,"url":"https://github.com/ubaidrmn/risc-v-assembly","last_synced_at":"2025-10-29T00:15:11.202Z","repository":{"id":190739160,"uuid":"683258319","full_name":"ubaidrmn/RISC-V-assembly","owner":"ubaidrmn","description":"RISC-V assembly code I wrote as part of my COAL course at UIT University.","archived":false,"fork":false,"pushed_at":"2023-08-26T02:46:31.000Z","size":15,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-04-02T06:19:17.669Z","etag":null,"topics":["assembly-language","processor-architecture","riscv","rv32i"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ubaidrmn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2023-08-26T02:14:08.000Z","updated_at":"2025-03-23T10:28:34.000Z","dependencies_parsed_at":"2023-08-26T06:15:13.277Z","dependency_job_id":null,"html_url":"https://github.com/ubaidrmn/RISC-V-assembly","commit_stats":null,"previous_names":["ubaidrmn/riscv-assembly","ubaidrmn/risc-v-assembly"],"tags_count":null,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ubaidrmn%2FRISC-V-assembly","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ubaidrmn%2FRISC-V-assembly/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ubaidrmn%2FRISC-V-assembly/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ubaidrmn%2FRISC-V-assembly/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ubaidrmn","download_url":"https://codeload.github.com/ubaidrmn/RISC-V-assembly/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246763893,"owners_count":20829806,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly-language","processor-architecture","riscv","rv32i"],"created_at":"2025-04-02T06:19:19.237Z","updated_at":"2025-10-05T03:53:53.905Z","avatar_url":"https://github.com/ubaidrmn.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# riscv-assembly\n\nThis repository includes RISC-V assembly code I wrote as part of my COAL course at UIT University. The `processor-design.circ` is a logisim file that includes a RV32I processor design with I,R,B, and S type instructions designed by me for the final exam.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fubaidrmn%2Frisc-v-assembly","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fubaidrmn%2Frisc-v-assembly","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fubaidrmn%2Frisc-v-assembly/lists"}