{"id":13427725,"url":"https://github.com/ucb-bar/riscv-mini","last_synced_at":"2025-03-16T00:32:01.555Z","repository":{"id":37706298,"uuid":"69501272","full_name":"ucb-bar/riscv-mini","owner":"ucb-bar","description":"Simple RISC-V 3-stage Pipeline in Chisel","archived":false,"fork":false,"pushed_at":"2024-06-03T13:50:40.000Z","size":1359,"stargazers_count":526,"open_issues_count":6,"forks_count":106,"subscribers_count":40,"default_branch":"main","last_synced_at":"2024-08-01T01:27:44.683Z","etag":null,"topics":["chisel","riscv","rtl"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ucb-bar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2016-09-28T20:30:13.000Z","updated_at":"2024-08-01T01:27:44.683Z","dependencies_parsed_at":"2024-03-11T14:44:15.731Z","dependency_job_id":null,"html_url":"https://github.com/ucb-bar/riscv-mini","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-mini","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-mini/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-mini/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-mini/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ucb-bar","download_url":"https://codeload.github.com/ucb-bar/riscv-mini/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":221631812,"owners_count":16855012,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","riscv","rtl"],"created_at":"2024-07-31T01:00:39.351Z","updated_at":"2024-10-27T05:30:20.928Z","avatar_url":"https://github.com/ucb-bar.png","language":"Scala","funding_links":[],"categories":["Scala","CPU RISC-V","Open Source implementations","Open Source Core Implementations","Open Source Implementations"],"sub_categories":["网络服务_其他","Cores"],"readme":"# riscv-mini\n\nAuthor: Donggyu Kim (dgkim@eecs.berkeley.edu)\n\n`riscv-mini` is a simple RISC-V 3-stage pipeline written in Chisel. It has been a crucial example in various project developments,\nincluding [Chisel3](https://github.com/ucb-bar/chisel3.git), [FIRRTL](https://github.com/ucb-bar/firrtl.git),\n[Strober](https://bar.eecs.berkeley.edu/projects/strober.html), simulation and verification methodologies.\nIt implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7.\nUnlike other simple pipelines, it also contains simple instruction and data caches.\n\nNote that a real-world processor is not the goal of `riscv-mini`.\nIt is developed as an intermediate example before diving into [rocket-chip](https://github.com/freechipsproject/rocket-chip). \n\n## Datapath Diagram\n![pipeline](diagram.png)\n\n## Getting Started\n\n    $ git clone https://github.com/ucb-bar/riscv-mini.git\n    $ cd riscv-mini\n    $ make            # generate firrtl \u0026 verilog files in generated-src\n    \nThe verilog output file can be used for verilator simulation or the ASIC tool flow.\n    \n## Running Verilator Simulation\n\nFirst, generate the verilator binary:\n\n    $ make verilator\n    \nThis will generate `VTile` in the top-level directory.\n\nNow, you can run verilator simulation for a given hex file as follows:\n\n    $ ./VTile \u003chex file\u003e [\u003cvcd file\u003e 2\u003e \u003clog file\u003e]\n    \n`\u003cvcd file\u003e` and the pipe to `\u003clog file\u003e` are optional. The waveform is dumped to `dump.vcd` and the execution trace is printed in the screen by default.\n\nThe following command runs the whole test hex files in verilator and dumps the traces and the waveforms to the 'outputs' directory:\n\n    $ make run-tests\n\n## Unit and Integration Tests with `sbt`\n\n`riscv-mini` provides synthesizable unit \u0026 integration tests.\nTheres are six sets of unit tests(`ALUTests`, `BrCondTests`, `ImmGenTests`, `CSRTests`, `CacheTests`, `DatapathTests`),\nrunning user-defined test vectors.\nTo execute them, first launch sbt with `make sbt` and run:\n\n    \u003e testOnly mini.[testname]\n  \nThere are also six sets of integration tests, running the hex files from [riscv-tests](https://github.com/riscv/riscv-tests).\nTo execute them, also launch `sbt` and run:\n\n    \u003e testOnly mini.[Core|Tile][Simple|ISA|Bmark]Tests\n    \n`Core` only contains the datapath and the control unit, while `Tile` also contains I$ and D$. `Simple` only runs `rv32ui-p-simple`,\n`ISA` runs the whole ISA tests, and `Bmark` runs five benchmarks(`median`, `multiply`, `qsort`, `towers`, `vvadd`). \nNote that all tests in a set run in parallel.\n\nFinally, to run all the tests, just in sbt:\n\n    \u003e test\n    \n## Running Your Own Program on `riscv-mini`\n\nAt this point, you may want to implement and exeucte your custom application on `riscv-mini`. In this case, you need to install RISC-V tools for priv 1.7. This repo provides a script to install the correct version of tools. Run the script as follows:\n\n    $ export RISCV=\u003cpath to riscv tools for priv 1.7\u003e\n    $ ./build-riscv-tools\n    \nIt takes a while to install the toolchain, so please be patient.\n\nThis repo also provides a template for your own program in `custom-bmark`. Add your c or assembly code and edit `Makefile`. Next, to compile you program, run `make` in `custom-bmark` to generate the binary, dump, and the hex files. Finally, run the following command in the base directory:\n\n    $ make run-custom-bmark\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fucb-bar%2Friscv-mini","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fucb-bar%2Friscv-mini","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fucb-bar%2Friscv-mini/lists"}