{"id":13599943,"url":"https://github.com/ucb-bar/riscv-sodor","last_synced_at":"2025-05-15T02:06:24.609Z","repository":{"id":9574859,"uuid":"11488873","full_name":"ucb-bar/riscv-sodor","owner":"ucb-bar","description":"educational microarchitectures for risc-v isa","archived":false,"fork":false,"pushed_at":"2025-03-07T19:21:17.000Z","size":8092,"stargazers_count":711,"open_issues_count":14,"forks_count":158,"subscribers_count":81,"default_branch":"master","last_synced_at":"2025-04-09T06:01:41.759Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ucb-bar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2013-07-17T22:10:42.000Z","updated_at":"2025-04-04T03:47:59.000Z","dependencies_parsed_at":"2023-02-17T11:45:58.740Z","dependency_job_id":"bc8b33f4-7657-4eb3-84b9-61147edd0cb0","html_url":"https://github.com/ucb-bar/riscv-sodor","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-sodor","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-sodor/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-sodor/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ucb-bar%2Friscv-sodor/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ucb-bar","download_url":"https://codeload.github.com/ucb-bar/riscv-sodor/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254259370,"owners_count":22040819,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T17:01:20.578Z","updated_at":"2025-05-15T02:06:24.591Z","avatar_url":"https://github.com/ucb-bar.png","language":"Scala","funding_links":[],"categories":["Scala","Open Source Implementations","CPU RISC-V"],"sub_categories":["Cores","网络服务_其他"],"readme":"About The Sodor Processor Collection\n====================================\n\n**Note: This repo has been updated to be used with the [Chipyard](https://github.com/ucb-bar/chipyard) SoC Generator.**\n**For the old self-contained version of Sodor (which is no longer maintained), see https://github.com/ucb-bar/riscv-sodor/tree/sodor-old.**\n\nDiagrams: [Sodor Github wiki](https://github.com/ucb-bar/riscv-sodor/wiki)\n\nMore documentation: [Librecores Sodor wiki](https://github.com/librecores/riscv-sodor/wiki)\n\nDownstream development: [Librecores Sodor](https://github.com/librecores/riscv-sodor)\n\n\nThis repo has been put together to demonstrate a number of simple [RISC-V](http://riscv.org)\ninteger pipelines written in [Chisel](http://chisel.eecs.berkeley.edu):\n\n* 1-stage (essentially an ISA simulator)\n* 2-stage (demonstrates pipelining in Chisel)\n* 3-stage (uses sequential memory; supports both Harvard and Princeton versions)\n* 5-stage (can toggle between fully bypassed or fully interlocked)\n* \"bus\"-based micro-coded implementation\n\nAll of the cores implement the RISC-V 32b integer base user-level ISA (RV32I)\nversion 2.0. None of the cores support virtual memory, and thus only implement\nthe Machine-level (M-mode) of the Privileged ISA v1.10 .\n\nAll processors talk to a simple scratchpad memory (asynchronous,\nsingle-cycle), with no backing outer memory (the 3-stage is the exception\n\\- its scratchpad is synchronous). Programs are loaded in via JTAG or TSI,\nscratchpads 3-port memories (instruction, data, debug).\n\nThis repository is set up to use the Verilog file generated by Chisel3 which is fed\nto Verilator along with a test harness in C++ to generate and run the Sodor emulators.\n\nThis repo works great as an undergraduate lab (and has been used by Berkeley's\nCS152 class for 3 semesters and counting). See doc/ for an example, as well as\nfor some processor diagrams. Be careful though - admittedly some of those\ndocuments may become dated as things like the Privileged ISA evolve.\n\n\n\nGetting the repo and Building the processor emulators\n=====================================================\n\nThis repo is **NOT** a self-running repository. Please follow the instruction in \nhttps://chipyard.readthedocs.io/en/latest/ to set up Chipyard and simulate Sodor cores.\n\nFAQ\n===\n\n*What is the goal of these cores?*\n\nFirst and foremost, to provide a set of easy to understand cores that users can\neasily modify and play with. Sodor is useful both as a quick introduction to\nthe [RISC-V ISA](http://riscv.org) and to the hardware construction language\n[Chisel3](http://chisel.eecs.berkeley.edu).\n\n*Are there any diagrams of these cores?*\n\nDiagrams of some of the processors can be found either in the\n[Sodor Github wiki](https://github.com/ucb-bar/riscv-sodor/wiki), in doc/,\nor in doc/lab1.pdf.  A more comprehensive write-up on the micro-code implementation can\nbe found at the [CS152 website](http://inst.eecs.berkeley.edu/~cs152/sp12/handouts/microcode.pdf).\n\n\n*How do I generate Verilog code for use on a FPGA?*\n\nChisel3 outputs verilog by default which can be generated by\n```bash\ncd emulator/rv32_1stage\nmake generated-src/Top.v\n```\n\n*I want to help! Where do I go?*\n\nYou can participate in the Sodor conversation on [gitter](https://gitter.im/librecores/riscv-sodor). Downstream development is also taking place at [Librecores](https://github.com/librecores/riscv-sodor). Major milestones will be pulled back here. Check it out! We also accept pull requests here!\n\nTODO\n----\n\nHere is an informal list of things that would be nice to get done. Feel free to\ncontribute!\n\n* Reduce the port count on the scratchpad memory by having the HTIF port\n  share one of the cpu ports.\n* Provide a Verilog test harness, and put the 3-stage on a FPGA.\n* Add support for the ma_addr, ma_fetch ISA tests. This requires detecting\n  misaligned address exceptions.\n* Greatly cleanup the common/csr.scala file, to make it clearer and more\n  understandable.\n* Refactor the stall, kill, fencei, and exception logic of the 5-stage to be\n  more understandable.\n* Update the u-code to properly handle illegal instructions (rv32mi-p-illegal)\n  and to properly handle exceptions generated by the CSR file (rv32mi-p-csr).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fucb-bar%2Friscv-sodor","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fucb-bar%2Friscv-sodor","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fucb-bar%2Friscv-sodor/lists"}