{"id":20925782,"url":"https://github.com/udxs/hdl-vlsi-exprs","last_synced_at":"2026-03-19T18:04:35.306Z","repository":{"id":116759637,"uuid":"419579962","full_name":"UDXS/hdl-vlsi-exprs","owner":"UDXS","description":"A collection of select Verilog/Innovus (GDS2-only) experiments","archived":false,"fork":false,"pushed_at":"2022-08-31T11:55:37.000Z","size":540,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-01-19T18:14:10.093Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/UDXS.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-10-21T04:26:24.000Z","updated_at":"2022-06-23T19:34:46.000Z","dependencies_parsed_at":null,"dependency_job_id":"a5a847fe-efcd-4ca0-b31b-26f8653c9da6","html_url":"https://github.com/UDXS/hdl-vlsi-exprs","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/UDXS%2Fhdl-vlsi-exprs","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/UDXS%2Fhdl-vlsi-exprs/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/UDXS%2Fhdl-vlsi-exprs/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/UDXS%2Fhdl-vlsi-exprs/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/UDXS","download_url":"https://codeload.github.com/UDXS/hdl-vlsi-exprs/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243318758,"owners_count":20272144,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-18T20:34:52.169Z","updated_at":"2025-12-30T01:58:03.496Z","avatar_url":"https://github.com/UDXS.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# HDL/VLSI Experiments\nA collection of Verilog/Innovus experiments.\n\n## ASQRT\nFlexible 32-bit square-root implementation. Implemented with Cadence Genus/Innovus and FreePDK45. Lacking formal verification.\n\n## asterix-emu\nSimple SPI-to-UART bridge emulating the Sharp LS013B7DH05 MiP display for smartwatch development purposes\nwith the Asterix RebbleOS platform and the Nordic nRF52840DK. There is a really small serial reader program \nin asterix-emu/viewer.\n\n## aTwo\nSimple 8-bit CPU using someone else's ISA. Implemented with Cadence Genus/Innovus and FreePDK45. Lacking any verification.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fudxs%2Fhdl-vlsi-exprs","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fudxs%2Fhdl-vlsi-exprs","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fudxs%2Fhdl-vlsi-exprs/lists"}