{"id":19924289,"url":"https://github.com/ultraembedded/altor32","last_synced_at":"2026-03-06T05:39:33.142Z","repository":{"id":19564232,"uuid":"22813322","full_name":"ultraembedded/altor32","owner":"ultraembedded","description":"AltOr32 - Alternative Lightweight OpenRisc CPU","archived":false,"fork":false,"pushed_at":"2015-12-17T02:07:36.000Z","size":321,"stargazers_count":12,"open_issues_count":2,"forks_count":7,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-01-12T00:25:16.112Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-08-10T16:33:22.000Z","updated_at":"2024-11-29T06:48:15.000Z","dependencies_parsed_at":"2022-08-23T19:00:35.909Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/altor32","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Faltor32","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Faltor32/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Faltor32/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Faltor32/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/altor32/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241351290,"owners_count":19948640,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-12T22:16:56.931Z","updated_at":"2026-03-06T05:39:33.050Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"AltOr32 - Alternative Lightweight OpenRisc CPU\n==============================================\n\nAltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project. \nInstructions \u0026 registers relating to Vector, floating-point, 64-bit extensions, MMU \u0026 Cache have been omitted. \nThe aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology. \n\nThis design implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation. \n\nAltOR32 does not make use of delay slots, unlike the original OpenRisc implementation. \nDue to this, the or1knd toolchain is required.\n\n##### Toolchain\n\nThe 'or1knd' toolchain is required for this target. \n\nTo build from source: \n\n`git clone git://github.com/openrisc/or1k-src.git`\n`git clone git://github.com/openrisc/or1k-gcc.git`\n\nBuild the first set of tools, binutils etc:\n\n`../or1k-src/configure --target=or1knd-elf --prefix=/opt/or1k-toolchain --enable-shared --disable-itcl --disable-tk --disable-tcl --disable-winsup --disable-libgui --disable-rda --disable-sid --disable-sim --disable-gdb --with-sysroot --disable-newlib --disable-libgloss --disable-werror` \n`make`\n`make install`\n\nBuild gcc:\n\n`../or1k-gcc/configure --target=or1knd-elf --prefix=/opt/or1k-toolchain --enable-languages=c --disable-shared --disable-libssp --disable-werror`\n`make`\n`make install`\n\n##### Verilator\n\nThe project contains a Verilator cycle accurate model of the CPU which can execute the same code as the simulator. Waveforms can be outputted and viewed in GTKWave. \n\n##### Current Status\n\n- Pipelined Verilog core with optional instruction \u0026 data cache. \n- Synthesizes to ~100MHz on a Xilinx Spartan 6 LX9 -3 \n- Harvard architecture (separate instruction \u0026 data cache / memory interfaces). \n- Support for interrupts \u0026 tick timer. \n- Also contains a smaller non-pipelined 'lite' version.\n\n##### Instruction Set Simulator\n\n- A simple simulator for OpenRisc instructions. \n- Able to execute OpenRisc 1000 (ORBIS32) code compiled with the following options: \n-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext \n- Extensible\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Faltor32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Faltor32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Faltor32/lists"}