{"id":13649363,"url":"https://github.com/ultraembedded/biriscv","last_synced_at":"2025-04-04T07:05:22.806Z","repository":{"id":40628202,"uuid":"239628306","full_name":"ultraembedded/biriscv","owner":"ultraembedded","description":"32-bit Superscalar RISC-V CPU","archived":false,"fork":false,"pushed_at":"2021-09-18T17:41:41.000Z","size":3121,"stargazers_count":975,"open_issues_count":21,"forks_count":162,"subscribers_count":32,"default_branch":"master","last_synced_at":"2025-03-28T06:04:29.438Z","etag":null,"topics":["artix-7","asic","branch-prediction","coremark","cpu","fpga","in-order","linux","pipelined-processors","risc-v","riscv-linux","rv32i","rv32im","superscalar","verilator","verilog","xilinx"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-02-10T22:38:34.000Z","updated_at":"2025-03-26T17:41:34.000Z","dependencies_parsed_at":"2022-07-16T10:30:32.596Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/biriscv","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fbiriscv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fbiriscv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fbiriscv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fbiriscv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/biriscv/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247135142,"owners_count":20889420,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["artix-7","asic","branch-prediction","coremark","cpu","fpga","in-order","linux","pipelined-processors","risc-v","riscv-linux","rv32i","rv32im","superscalar","verilator","verilog","xilinx"],"created_at":"2024-08-02T01:04:58.033Z","updated_at":"2025-04-04T07:05:22.788Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","readme":"# biRISC-V - 32-bit dual issue RISC-V CPU\n\nGithub: [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)\n\n![biRISC-V](docs/biRISC-V.png)\n\n## Features\n* 32-bit RISC-V ISA CPU core.\n* Superscalar (dual-issue) in-order 6 or 7 stage pipeline.\n* Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).\n* Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS).\n* 64-bit instruction fetch, 32-bit data access.\n* 2 x integer ALU (arithmetic, shifters and branch units).\n* 1 x load store unit, 1 x out-of-pipeline divider.\n* Issue and complete up to 2 independent instructions per cycle.\n* Supports user, supervisor and machine mode privilege levels.\n* Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.\n* Implements base ISA spec [v2.1](docs/riscv_isa_spec.pdf) and privileged ISA spec [v1.11](docs/riscv_privileged_spec.pdf).\n* Verified using [Google's RISCV-DV](https://github.com/google/riscv-dv) random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).\n* Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.\n* Configurable number of pipeline stages, result forwarding options, and branch prediction resources.\n* Synthesizable Verilog 2001, Verilator and FPGA friendly.\n* Coremark:  **4.1 CoreMark/MHz**\n* Dhrystone: **1.9 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)\n\n*A sequence showing execution of 2 instructions per cycle;*\n![Dual-Issue](docs/dual_issue.png)\n\n## Documentation\n* [Configuration](docs/configuration.md)\n* [Booting Linux](docs/linux.md)\n* [Integration](docs/integration.md)\n* [Custom Features](docs/custom.md)\n\n## Similar Cores\n* [SiFive E76](https://www.sifive.com/cores/e76)\n  * RV32IMAFC\n  * Dual issue in-order 8 stage pipeline\n  * 4 ALU units (2 early, 2 late)\n  * :heavy_multiplication_x: *Commercial closed source core/$$*\n* [WD SweRV RISC-V Core EH1](https://github.com/chipsalliance/Cores-SweRV)\n  * RV32IMC\n  * Dual issue in-order 9 stage pipeline\n  * 4 ALU units (2 early, 2 late)\n  * :heavy_multiplication_x: *System Verilog + auto signal hookup*\n  * :heavy_multiplication_x: *No data cache option*\n  * :heavy_multiplication_x: *Not able to boot Linux*\n\n## Project Aims\n* Boot Linux all the way to a functional userspace environment. :heavy_check_mark:\n* Achieve competitive performance for this class of in-order machine (i.e. aim for 80% of WD SweRV CoreMark score). :heavy_check_mark:\n* Reasonable PPA / FPGA resource friendly. :heavy_check_mark:\n* Fit easily onto cheap hobbyist FPGAs (e.g. Xilinx Artix 7) without using all LUT resources and synthesize \u003e 50MHz. :heavy_check_mark:\n* Support various cache and TCM options. :heavy_check_mark:\n* Be constructed using readable, maintainable and documented IEEE 1364-2001 Verilog. :heavy_check_mark:\n* Simulate in open-source tools such as Verilator and Icarus Verilog. :heavy_check_mark:\n* *In later releases, add support for atomic extensions.*\n\n*Booting the stock Linux 5.0.0-rc8 kernel built for RV32IMA to userspace on a Digilent Arty Artix 7 with biRISC-V (with atomic instructions emulated in the bootloader);*\n![Linux-Boot](docs/linux-boot.png)\n\n## Prior Work\nBased on my previous work;\n* Github: [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)\n\n## Getting Started\n\n#### Cloning\n\nTo clone this project and its dependencies;\n\n```\ngit clone --recursive https://github.com/ultraembedded/biriscv.git\n\n```\n\n#### Running Helloworld\n\nTo run a simple test image on the core RTL using Icarus Verilog;\n\n```\n# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)\nsudo apt-get install iverilog\n\n# [or] Install Icarus Verilog (Redhat / Centos)\n#sudo yum install iverilog\n\n# Run a simple test image (test.elf)\ncd tb/tb_core_icarus\nmake\n```\n\nThe expected output is;\n```\nStarting bench\nVCD info: dumpfile waveform.vcd opened for output.\n\nTest:\n1. Initialised data\n2. Multiply\n3. Divide\n4. Shift left\n5. Shift right\n6. Shift right arithmetic\n7. Signed comparision\n8. Word access\n9. Byte access\n10. Comparision\n```\n\n#### Configuration\n\n| Param Name                | Valid Range          | Description                                   |\n| ------------------------- |:--------------------:| ----------------------------------------------|\n| SUPPORT_SUPER             | 1/0                  | Enable supervisor / user privilege levels.    |\n| SUPPORT_MMU               | 1/0                  | Enable basic memory management unit.          |\n| SUPPORT_MULDIV            | 1/0                  | Enable HW multiply / divide (RV-M).           |\n| SUPPORT_DUAL_ISSUE        | 1/0                  | Support superscalar operation.                |\n| SUPPORT_LOAD_BYPASS       | 1/0                  | Support load result bypass paths.             |\n| SUPPORT_MUL_BYPASS        | 1/0                  | Support multiply result bypass paths.         |\n| SUPPORT_REGFILE_XILINX    | 1/0                  | Support Xilinx optimised register file.       |\n| SUPPORT_BRANCH_PREDICTION | 1/0                  | Enable branch prediction structures.          |\n| NUM_BTB_ENTRIES           | 2 -                  | Number of branch target buffer entries.       |\n| NUM_BTB_ENTRIES_W         | 1 -                  | Set to log2(NUM_BTB_ENTRIES).                 |\n| NUM_BHT_ENTRIES           | 2 -                  | Number of branch history table entries.       |\n| NUM_BHT_ENTRIES_W         | 1 -                  | Set to log2(NUM_BHT_ENTRIES_W).               |\n| BHT_ENABLE                | 1/0                  | Enable branch history table based prediction. |\n| GSHARE_ENABLE             | 1/0                  | Enable GSHARE branch prediction algorithm.    |\n| RAS_ENABLE                | 1/0                  | Enable return address stack prediction.       |\n| NUM_RAS_ENTRIES           | 2 -                  | Number of return stack addresses supported.   |\n| NUM_RAS_ENTRIES_W         | 1 -                  | Set to log2(NUM_RAS_ENTRIES_W).               |\n| EXTRA_DECODE_STAGE        | 1/0                  | Extra decode pipe stage for improved timing.  |\n| MEM_CACHE_ADDR_MIN        | 32'h0 - 32'hffffffff | Lowest cacheable memory address.              |\n| MEM_CACHE_ADDR_MAX        | 32'h0 - 32'hffffffff | Highest cacheable memory address.             |\n","funding_links":[],"categories":["Verilog","CPU RISC-V","Applications"],"sub_categories":["网络服务_其他"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fbiriscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fbiriscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fbiriscv/lists"}