{"id":19924300,"url":"https://github.com/ultraembedded/core_dbg_bridge","last_synced_at":"2026-02-14T10:31:08.466Z","repository":{"id":38449258,"uuid":"201753306","full_name":"ultraembedded/core_dbg_bridge","owner":"ultraembedded","description":"UART -\u003e AXI Bridge","archived":false,"fork":false,"pushed_at":"2021-07-01T16:41:44.000Z","size":22,"stargazers_count":63,"open_issues_count":0,"forks_count":20,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-09-07T05:44:37.248Z","etag":null,"topics":["axi4","fpga","uart","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-2.1","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-08-11T11:01:15.000Z","updated_at":"2025-08-17T15:58:56.000Z","dependencies_parsed_at":"2022-08-19T02:23:13.724Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/core_dbg_bridge","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_dbg_bridge","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dbg_bridge","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dbg_bridge/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dbg_bridge/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dbg_bridge/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_dbg_bridge/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dbg_bridge/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29442720,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-14T10:17:46.583Z","status":"ssl_error","status_checked_at":"2026-02-14T10:17:22.534Z","response_time":53,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["axi4","fpga","uart","verilog"],"created_at":"2024-11-12T22:16:59.756Z","updated_at":"2026-02-14T10:31:08.447Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### UART -\u003e AXI Debug Bridge\n\nGithub:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/dbg_bridge)\n\nThis component provides a bridge from a standard UART interface (8N1) to a AXI4 bus master \u0026 GPIO interface.  \nThis can be very useful for FPGA dev boards featuring a FTDI UART interface where loading memories, peeking, poking SoC state is required.\n\n##### Testing\n\nUsed extensively on various Xilinx FPGAs over the years.\n\n##### Configuration\n* CLK_FREQ - Clock (clk_i) frequency (in Hz).\n* UART_SPEED - UART baud rate (bps)\n* AXI_ID - AXI ID to be used for transactions\n\n##### Software\nIncluded python based utils provide peek and poke access, plus binary load / dump support.\n\nExamples:\n```\n# Read a memory location (0x0)\n./sw/peek.py -d /dev/ttyUSB1 -b 115200 -a 0x0\n\n# Write a memory word (0x0 = 0x12345678)\n./sw/poke.py -d /dev/ttyUSB1 -b 115200 -a 0x0 -v 0x12345678\n``` ","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_dbg_bridge","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_dbg_bridge","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_dbg_bridge/lists"}