{"id":19924282,"url":"https://github.com/ultraembedded/core_dvi_framebuffer","last_synced_at":"2025-03-01T10:25:39.638Z","repository":{"id":81709302,"uuid":"273698307","full_name":"ultraembedded/core_dvi_framebuffer","owner":"ultraembedded","description":"Minimal DVI / HDMI Framebuffer","archived":false,"fork":false,"pushed_at":"2020-08-09T14:35:07.000Z","size":79,"stargazers_count":78,"open_issues_count":0,"forks_count":12,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-01-12T00:25:15.755Z","etag":null,"topics":["axi4","dvi","fpga","framebuffer","hdmi","verilog","video","xilinx-fpga"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-06-20T11:52:20.000Z","updated_at":"2024-12-02T02:41:10.000Z","dependencies_parsed_at":null,"dependency_job_id":"789e222d-f570-4dd9-8d90-b84aa14bbe4e","html_url":"https://github.com/ultraembedded/core_dvi_framebuffer","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dvi_framebuffer","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dvi_framebuffer/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dvi_framebuffer/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_dvi_framebuffer/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_dvi_framebuffer/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241351313,"owners_count":19948647,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["axi4","dvi","fpga","framebuffer","hdmi","verilog","video","xilinx-fpga"],"created_at":"2024-11-12T22:16:56.487Z","updated_at":"2025-03-01T10:25:39.625Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### Minimal DVI / HDMI Framebuffer\n\nGithub:   [https://github.com/ultraembedded/core_dvi_framebuffer](https://github.com/ultraembedded/core_dvi_framebuffer)\n\nThis component allows the addition of a DVI/HDMI output to your FPGA project.  \nThe IP fetches pixel data from an external AXI-4 memory target and converts to a TMDS suitable for driving DVI or HDMI (DVI mode) outputs from a FPGA.\n\n![Block Diagram](docs/block_diagram.png)\n\nBased around [Mike Field's](https://github.com/hamsternz) TMDS encoder code.\n\n#### Features\n\n* HDMI / DVI TMDS output.\n* RGB565 input format.\n* AXI-4 bus master with burst support.\n* 4KB pixel data prefetch FIFO (which map to BlockRAMs in Xilinx FPGAs).\n* AXI-4 Lite register interface with programmable framebuffer fetch address, enable, interrupt control.\n* Start of frame interrupt output.\n* Configurable display resolution (640x480, 800x600, 1280x720, 1920x1080).\n* Works with the Linux 'simple-framebuffer' driver.\n\n#### Interfaces\n\n| Name          | Description                                                           |\n| ------------- | --------------------------------------------------------------------- |\n| clk_i         | Clock input - must be suitable for the configured res/refresh rate.   |\n| clk_x5_i      | Clock input x 5.                                                      |\n| rst_i         | Async reset, active-high.                                             |\n| cfg_*         | AXI-4 Lite configuration port (optional if VIDEO_ENABLE=1).           |\n| outport_*     | AXI4 master interface for pixel fetch data.                           |\n| intr_o        | Active high interrupt output (single cycle strobe).                   |\n\n#### Params\n\n| Name          | Default     | Description                                                    |\n| ------------- | ----------- | -------------------------------------------------------------- |\n| VIDEO_WIDTH   | 800         | Display resolution (H).                                        |\n| VIDEO_HEIGHT  | 600         | Display resolution (V).                                        |\n| VIDEO_REFRESH | 72          | Display refresh rate.                                          |\n| VIDEO_ENABLE  | 1           | Pixel fetch enable after reset (changeable via AXI-4L regif).  |\n| VIDEO_FB_RAM  | 32'h3000000 | Framebuffer base address (changeable via AXI-4L regif).        |\n\n#### Linux Framebuffer\n\nExample Linux DTS configuration with the framebuffer located @ 0x300_0000 and 800x600 display resolution;\n```\n    framebuffer {\n      compatible = \"simple-framebuffer\";\n      reg = \u003c0x3000000 (800 * 600 * 2)\u003e;\n      width = \u003c800\u003e;\n      height = \u003c600\u003e;\n      stride = \u003c(800 * 2)\u003e;\n      format = \"r5g6b5\";\n    }; \n```\n\n#### Testing\nTested on a Xilinx Artix 7 (Digilent Arty A7) with Dell U2515 monitor and a LG LCD TV with various resolutions.\nUsed with the Linux Kernel 'simple-framebuffer' driver.\n\n#### References\n* [TMDS Encoding](https://en.wikipedia.org/wiki/Transition-minimized_differential_signaling)\n* [DVI Interface](https://en.wikipedia.org/wiki/Digital_Visual_Interface)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_dvi_framebuffer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_dvi_framebuffer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_dvi_framebuffer/lists"}