{"id":19924296,"url":"https://github.com/ultraembedded/core_enet","last_synced_at":"2025-03-01T10:25:33.803Z","repository":{"id":81709364,"uuid":"423216890","full_name":"ultraembedded/core_enet","owner":"ultraembedded","description":"Ethernet MAC 10/100 Mbps","archived":false,"fork":false,"pushed_at":"2021-10-31T18:55:45.000Z","size":18,"stargazers_count":24,"open_issues_count":0,"forks_count":5,"subscribers_count":8,"default_branch":"main","last_synced_at":"2025-01-12T00:25:19.605Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-10-31T17:36:22.000Z","updated_at":"2024-08-16T15:41:24.000Z","dependencies_parsed_at":null,"dependency_job_id":"2e431462-bb15-4556-ba78-9559ebadead5","html_url":"https://github.com/ultraembedded/core_enet","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_enet","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_enet/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_enet/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_enet/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_enet/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241351262,"owners_count":19948637,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-12T22:16:59.374Z","updated_at":"2025-03-01T10:25:33.792Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### Ethernet MAC 10/100 Mbps\n\nGithub:   [https://github.com/ultraembedded/core_enet](https://github.com/ultraembedded/core_enet)\n\nThis component is a very basic 10/100Mbps Ethernet MAC.  \nThis Ethernet NIC operates as a memory-mapped peripheral.  \nIt does not feature a DMA interface, hence is low performance / CPU intensive to use, but it is, however, very small and simple.  \nThe register interface happens to have a similar programming model to the Xilinx EmacLite core, hence can make use of the existing Linux Kernel driver (xilinx_emaclite.c).\n\n##### Features\n* Support for full-duplex 10/100Mbps Ethernet.\n* Wishbone B4 pipelined interface.\n* Programmable MAC address for receive filtering.\n* 2 x Tx Ping Pong buffers (4KB total).\n* 2 x Rx Ping Pong buffers (4KB total).\n* MII Ethernet PHY interface (4-bit mode).\n* Interrupt output (on Tx space / Rx ready).\n\n##### Limitations\n* Half-duplex mode not implemented (it does not currently implement CSMA/CD required for well-behaved half-duplex mode).\n* MDIO requires GPIOs (use SW MDIO GPIO in the Linux Kernel).\n\n##### Size\nFor a Xilinx 7 series device;\n```\n- Slice LUTs:      534\n- Slice Registers: 543\n- BlockRAM:        4\n```\n\n##### Testing\nVerified under simulation then tested on FPGA using Linux 5.14.3 with ping, iperf, wget, tftp.\n\n##### Configuration\n* Top Module: enet.v\n* parameter PROMISCUOUS        - If set to 0, use MAC address filtering (broadcast, or local addr).\n* parameter DEFAULT_MAC_ADDR_L - Bytes 0 - 3 of the default MAC address\n* parameter DEFAULT_MAC_ADDR_H - Bytes 4 - 5 of the default MAC address\n\n##### DTS\nThe following Linux DTS entry should work for this core (change the base address and interrupt config as required);\n```\n   enet: ethernet@95000000 {\n        compatible = \"xlnx,xps-ethernetlite-3.00.a\";\n        device_type = \"network\";\n        interrupts = \u003c4\u003e;\n        local-mac-address = [00 00 BE AF FE AD];\n        reg = \u003c0x95000000 0x10000\u003e;\n        xlnx,duplex = \u003c0x1\u003e;\n        xlnx,rx-ping-pong = \u003c0x1\u003e;\n        xlnx,tx-ping-pong = \u003c0x1\u003e;\n    };\n```\n\n##### References\n* [MII Interface](https://en.wikipedia.org/wiki/Media-independent_interface)\n* [LogiCORE IP AXI Ethernet Lite MAC v3.0)](https://www.xilinx.com/support/documentation/ip_documentation/axi_ethernetlite/v3_0/pg135-axi-ethernetlite.pdf)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_enet","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_enet","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_enet/lists"}