{"id":19924288,"url":"https://github.com/ultraembedded/core_ftdi_bridge","last_synced_at":"2026-02-07T02:33:32.238Z","repository":{"id":81709419,"uuid":"202905213","full_name":"ultraembedded/core_ftdi_bridge","owner":"ultraembedded","description":"FTDI FT245 Style Synchronous/Asynchronous FIFO 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FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge\n\nGithub:   [https://github.com/ultraembedded/core_ftdi_bridge](https://github.com/ultraembedded/core_ftdi_bridge)\n\nThis component provides a bridge from the FTDI Asynchronous or Synchronous FIFO interface (such as found on the FT245 or FT2232) to an AXI4 master \u0026 GPIO interface.\n\nDevices such as the FT2232 must be switched into FIFO mode using the FT_PROG EEPROM programming tool from FTDI.  \nThe choice between asychronous and synchronous mode for FTDI devices which support it are done at runtime via the ftdi_set_bitmode API.\n\nThis component supports reads and writes down to byte level granularity.\n\n##### Supported FTDI devices\n\n| FTDI Device | Num Channels | Async FIFO Support | Sync FIFO Support |\n| ----------- | ------------ | ------------------ | ----------------- | \n| FT245B      |      1       |       True         |      False        |\n| FT245R      |      1       |       True         |      False        |\n| FT240X      |      1       |       True         |      False        |\n| FT2232D     |      2       |       True         |      False        |\n| FT232H      |      1       |       True         |      True         |\n| FT2232H     |      2       |       True         |      True         |\n\nSee [TN_167 FIFO Basics](https://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_167_FIFO_Basics.pdf) from FTDI for more details.\n\n##### Testing\n\nVerified under simulation and validated on FPGA.  \nUsed on the miniSpartan6+ board which uses the FTDI FT2232HL (asynchronous mode), and using an Xilinx Artix 7 board with FTDI FT2232HL (synchronous mode).\n\n##### Configuration\n* Top: ftdi_bridge\n* Clock: clk_i - Must be sourced from FTDI device for mode = SYNC\n* Reset: rst_i - Asynchronous, active high\n* parameter MODE - \"SYNC\" or \"ASYNC\" FT245 mode\n* parameter CLK_DIV - Clock divider (minimum is 2) (only valid for MODE=\"ASYNC\")\n* parameter GP_OUTPUTS - Number of GPIO outputs (1 - 8)\n* parameter GP_INPUTS - Number of GPIO inputs (1 - 8)\n* parameter AXI_ID - AXI ID to use\n\n##### Size / Speed\n\nFor asynchronous mode;\n* ~220 flops / 320 LUTs (Spartan 6)\n* ~200MHz on Xilinx Spartan 6 LX9 (speed -3)\n\nFor synchronous mode;\n* ~275 flops / 598 LUTs (Spartan 6)\n* ~165MHz on Xilinx Spartan 6 LX9 (speed -3)\n\n##### Example Instantiation\n\nThis example works well for Xilinx FPGAs;\n```\nwire [7:0] ftdi_data_in_w;\nwire [7:0] ftdi_data_out_w;\n\nftdi_bridge\n#(\n\t.MODE(\"SYNC\")\n)\nu_bridge\n(\n     .clk_i(ftdi_clk_i)\n    ,.rst_i(rst)\n\n    ,.mem_awvalid_o(...)\n    ,.mem_awaddr_o(...)\n    ,.mem_awid_o(...)\n    ,.mem_awlen_o(...)\n    ,.mem_awburst_o(...)\n    ,.mem_wvalid_o(...)\n    ,.mem_wdata_o(...)\n    ,.mem_wstrb_o(...)\n    ,.mem_wlast_o(...)\n    ,.mem_bready_o(...)\n    ,.mem_arvalid_o(...)\n    ,.mem_araddr_o(...)\n    ,.mem_arid_o(...)\n    ,.mem_arlen_o(...)\n    ,.mem_arburst_o(...)\n    ,.mem_rready_o(...)    \n    ,.mem_awready_i(...)\n    ,.mem_wready_i(...)\n    ,.mem_bvalid_i(...)\n    ,.mem_bresp_i(...)\n    ,.mem_bid_i(...)\n    ,.mem_arready_i(...)\n    ,.mem_rvalid_i(...)\n    ,.mem_rdata_i(...)\n    ,.mem_rresp_i(...)\n    ,.mem_rid_i(...)\n    ,.mem_rlast_i(...)\n\n    ,.ftdi_rxf_i(ftdi_rxf_i)\n    ,.ftdi_txe_i(ftdi_txe_i)\n    ,.ftdi_data_in_i(ftdi_data_in_w)\n    ,.ftdi_siwua_o(ftdi_siwua_o)\n    ,.ftdi_wrn_o(ftdi_wrn_o)\n    ,.ftdi_rdn_o(ftdi_rdn_o)\n    ,.ftdi_oen_o(ftdi_oen_o)\n    ,.ftdi_data_out_o(ftdi_data_out_w)\n\n);\n\nassign ftdi_data_in_w = ftdi_data_io;\nassign ftdi_data_io   = ftdi_oen_o ? ftdi_data_out_w : 8'hZZ;\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_ftdi_bridge","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_ftdi_bridge","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_ftdi_bridge/lists"}