{"id":19924286,"url":"https://github.com/ultraembedded/core_mmc","last_synced_at":"2026-03-07T04:02:52.242Z","repository":{"id":81709541,"uuid":"295549707","full_name":"ultraembedded/core_mmc","owner":"ultraembedded","description":"MMC (and derivative standards) host controller","archived":false,"fork":false,"pushed_at":"2020-09-14T22:37:52.000Z","size":17,"stargazers_count":23,"open_issues_count":0,"forks_count":3,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-03-01T10:25:15.850Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-09-14T22:08:42.000Z","updated_at":"2025-01-20T12:35:37.000Z","dependencies_parsed_at":null,"dependency_job_id":"5f09b167-f2af-4695-909d-2898e9fc3b60","html_url":"https://github.com/ultraembedded/core_mmc","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_mmc","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mmc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mmc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mmc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mmc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_mmc/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mmc/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30207393,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-07T03:24:23.086Z","status":"ssl_error","status_checked_at":"2026-03-07T03:23:11.444Z","response_time":53,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-12T22:16:56.708Z","updated_at":"2026-03-07T04:02:47.231Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### MMC (and derivative standards) Host Controller\n\nGithub:   [https://github.com/ultraembedded/core_mmc](https://github.com/ultraembedded/core_mmc)\n\nWork-in-progress - basically functional but not yet complete / robust.\n\n##### Features\n* 1-bit / 4-bit data modes.\n* Large sector buffer (for multiple sector reads or writes).\n* AXI-4 DMA.\n\n##### Current Bugs\n* DMA: Does not support card write mode (functions as read from card only).\n* Robustness: Not currently checking CRC7 / CRC16 on incoming responses.\n* Writes: Multi-sector write support is not correct.\n* AXI: Dubious combinatorial paths on AWVALID and WVALID.\n\n##### Testing\nExercised on the following FPGA boards;\n* Digilent Arty A7 (Xilinx Artix 7)\n* LambaConcept ECPIX-5 (Lattice ECP5)\n\n##### Register Map\n\n| Offset | Name | Description   |\n| ------ | ---- | ------------- |\n| 0x00 | MMC_CONTROL | [RW] Transfer Control Register |\n| 0x04 | MMC_CLOCK | [RW] Clock Configuration Register |\n| 0x08 | MMC_STATUS | [R] Transfer Status Register |\n| 0x0c | MMC_CMD0 | [RW] Command (first 32-bits) |\n| 0x10 | MMC_CMD1 | [RW] Command (subsequent 16-bits) |\n| 0x14 | MMC_RESP0 | [R] Response Register |\n| 0x18 | MMC_RESP1 | [R] Response Register |\n| 0x1c | MMC_RESP2 | [R] Response Register |\n| 0x20 | MMC_RESP3 | [R] Response Register |\n| 0x24 | MMC_RESP4 | [R] Response Register |\n| 0x28 | MMC_TX | [W] Data Transmit Register |\n| 0x2c | MMC_RX | [R] Data Receive Register |\n| 0x30 | MMC_DMA | [RW] DMA Target |\n\n##### Register: MMC_CONTROL\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31 | START | Start transfer. |\n| 30 | ABORT | Abort transfer. |\n| 29 | FIFO_RST | FIFO reset. |\n| 15:8 | BLOCK_CNT | Number of blocks (0=1, 1=2, ...) |\n| 5 | WRITE | Data write operation |\n| 4 | DMA_EN | DMA port enable |\n| 3 | WIDE_MODE | 4-bit data mode. |\n| 2 | DATA_EXP | Wait for data |\n| 1 | RESP136_EXP | Wait for response (R2). |\n| 0 | RESP48_EXP | Wait for response (~R2). |\n\n##### Register: MMC_CLOCK\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DIV | Clock divider |\n\n##### Register: MMC_STATUS\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 8 | CMD_IN | Command input line state |\n| 7:4 | DAT_IN | Data input line state |\n| 3 | FIFO_EMPTY | FIFO empty. |\n| 2 | FIFO_FULL | FIFO full. |\n| 1 | CRC_ERR | CRC error |\n| 0 | BUSY | Transfer active |\n\n##### Register: MMC_CMD0\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Command data. |\n\n##### Register: MMC_CMD1\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 15:0 | VALUE | Command data. |\n\n##### Register: MMC_RESP0\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Response data. |\n\n##### Register: MMC_RESP1\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Response data. |\n\n##### Register: MMC_RESP2\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Response data. |\n\n##### Register: MMC_RESP3\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Response data. |\n\n##### Register: MMC_RESP4\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Response data. |\n\n##### Register: MMC_TX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | Data |\n\n##### Register: MMC_RX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | Data |\n\n##### Register: MMC_DMA\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ADDR | Start address |\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_mmc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_mmc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_mmc/lists"}