{"id":19924277,"url":"https://github.com/ultraembedded/core_mpx","last_synced_at":"2026-03-03T18:32:37.525Z","repository":{"id":81709558,"uuid":"309163774","full_name":"ultraembedded/core_mpx","owner":"ultraembedded","description":"MPX is a open-source CPU which can execute code compiled for MIPS-I ISA","archived":false,"fork":false,"pushed_at":"2020-11-21T12:23:31.000Z","size":88,"stargazers_count":11,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-11-24T01:19:58.265Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"github":"ultraembedded"}},"created_at":"2020-11-01T18:43:23.000Z","updated_at":"2025-11-06T21:25:25.000Z","dependencies_parsed_at":null,"dependency_job_id":"3a4669f1-a01b-4f67-8473-e23e3febcbd7","html_url":"https://github.com/ultraembedded/core_mpx","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_mpx","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mpx","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mpx/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mpx/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mpx/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_mpx/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_mpx/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30054602,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-03T18:21:05.932Z","status":"ssl_error","status_checked_at":"2026-03-03T18:20:59.341Z","response_time":61,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-12T22:16:56.332Z","updated_at":"2026-03-03T18:32:37.502Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":["https://github.com/sponsors/ultraembedded"],"categories":[],"sub_categories":[],"readme":"# MPX\n\nGithub: [https://github.com/ultraembedded/core_mpx](https://github.com/ultraembedded/core_mpx)\n\nMPX is an open-source CPU which can execute code compiled for MIPS-I ISA (as per the MIPS R2000 / R3000 CPUs).\n\n*Disclaimer: I am not associated with MIPs Technologies Inc.  \nThe version of MIPS ISA implemented here is 30+ years old, so undoubtedly any patents related to it will have expired.  \nThis core was implemented using only publically available ISA documentation.*\n\nThis core is not a good starting point for new designs. You should consider using RISC-V based designs instead, as RISC-V is a cleaned up and more modern RISC ISA that is also open-source.\n\nI have designed multiple RISC-V cores that you should consider instead of MPX;\n* [https://github.com/ultraembedded/biriscv](https://github.com/ultraembedded/biriscv)\n* [https://github.com/ultraembedded/riscv](https://github.com/ultraembedded/riscv)\n\n## Rationale\nSo why design this core? Well... There are some interesting real-world products that featured MIPS R3000 CPUs such as the Sony Playstation 1, and there are ongoing efforts to recreate them in modern FPGA technology. \n\n## Overview\n![](docs/mpx_pipeline.png)\n\n## Features\n* 32-bit MIPS-I ISA compatible CPU core.\n* Simple 5-stage pipelined design.\n* Support for external co-processors (COP1 - 3).\n* Synthesizable Verilog 2001, Verilator and FPGA friendly.\n\nNote: This core does not have a built-in floating-point unit (COP1), however, one can be implemented and connected to the top-level ports of the design.\n\n## Status\nThis is a very early release of the RTL. There are likely to be bugs!\n\nKnown items on the TODO list are;\n* Implement faults on invalid instructions (RI) and arithmetic overflow (OV).\n* Optimise the instruction decoder to be smaller and have a shorter critical path.\n* Re-implement various bugs and quirks found in actual MIPS R2000/3000 designs.\n* Rework multiply/divide instructions to be non-blocking (the current implementation is faster than the original but blocking).\n* Rework the co-processor interfaces to reduce the CPU critical path.\n* More extensive verification is required.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_mpx","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_mpx","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_mpx/lists"}