{"id":19924287,"url":"https://github.com/ultraembedded/core_soc","last_synced_at":"2026-03-06T00:31:26.120Z","repository":{"id":81709573,"uuid":"201666736","full_name":"ultraembedded/core_soc","owner":"ultraembedded","description":"Basic Peripheral SoC (SPI, GPIO, Timer, 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returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","gpio","spi","timer","uart","verilog"],"created_at":"2024-11-12T22:16:56.709Z","updated_at":"2026-03-06T00:31:26.095Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","readme":"## Basic Peripheral SoC\n\nGithub:   [http://github.com/ultraembedded/core_soc](http://github.com/ultraembedded/core_soc)\n\nA basic SoC with Timer, UART, SPI, GPIO and Interrupt Controller peripherals.\n\n### Features\n* Multi-channel timer peripheral.\n* UART peripheral.\n* SPI (master mode) peripheral with 8 chip selects.\n* 32 I/O GPIO controller.\n* 3 external peripherals (AXI4-Lite interface).\n* Interrupt controller (combines peripheral IRQs into single IRQ).\n* AXI4-Lite slave interface.\n\n### Configuration\n* Top: core_soc\n* Clock: clk_i\n* Reset: rst_i - Asynchronous, active high\n* parameter CLK_FREQ - Clock speed (in Hz)\n* parameter BAUDRATE - UART baud rate (e.g. 115200)\n* parameter C_SCK_RATIO - SPI clock divider ratio for clk_i -\u003e spi_clk_o\n\n### Memory Map\n\n| Range                     | Description                                         |\n| ------------------------- | --------------------------------------------------- |\n| 0x0000_0000 - 0x00ff_ffff | Peripheral - IRQ controller                         |\n| 0x0100_0000 - 0x01ff_ffff | Peripheral - Timer                                  |\n| 0x0200_0000 - 0x02ff_ffff | Peripheral - UART                                   |\n| 0x0300_0000 - 0x03ff_ffff | Peripheral - SPI                                    |\n| 0x0400_0000 - 0x04ff_ffff | Peripheral - GPIO                                   |\n| 0x0500_0000 - 0x05ff_ffff | Peripheral - External 1                             |\n| 0x0600_0000 - 0x06ff_ffff | Peripheral - External 2                             |\n| 0x0700_0000 - 0x07ff_ffff | Peripheral - External 3                             |\n\n### Interrupt Sources\n\n| Index  | Source                      |\n| -------| --------------------------- |\n|   0    | Peripheral - Timer          |\n|   1    | Peripheral - UART           |\n|   2    | Peripheral - SPI            |\n|   3    | Peripheral - GPIO           |\n|   4    | Peripheral - External 1     |\n|   5    | Peripheral - External 2     |\n|   6    | Peripheral - External 3     |\n\n### Peripheral Register Map\n\n| Offset | Name | Description   |\n| ------ | ---- | ------------- |\n| 0x0000_0000 | IRQ_ISR | [RW] Interrupt Status Register |\n| 0x0000_0004 | IRQ_IPR | [R] Interrupt Pending Register |\n| 0x0000_0008 | IRQ_IER | [RW] Interrupt Enable Register |\n| 0x0000_000c | IRQ_IAR | [W] Interrupt Acknowledge Register |\n| 0x0000_0010 | IRQ_SIE | [W] Set Interrupt Enable bits |\n| 0x0000_0014 | IRQ_CIE | [W] Clear Interrupt Enable bits |\n| 0x0000_0018 | IRQ_IVR | [RW] Interrupt Vector Register |\n| 0x0000_001c | IRQ_MER | [RW] Master Enable Register |\n| 0x0100_0008 | TIMER_CTRL0 | [RW] Control |\n| 0x0100_000c | TIMER_CMP0 | [RW] Compare value (interrupt on match) |\n| 0x0100_0010 | TIMER_VAL0 | [RW] Current Value |\n| 0x0100_0014 | TIMER_CTRL1 | [RW] Control |\n| 0x0100_0018 | TIMER_CMP1 | [RW] Compare value (interrupt on match) |\n| 0x0100_001c | TIMER_VAL1 | [RW] Current Value |\n| 0x0200_0000 | ULITE_RX | [R] UART Data Register |\n| 0x0200_0004 | ULITE_TX | [W] UART Data Register |\n| 0x0200_0008 | ULITE_STATUS | [R] UART Status Register |\n| 0x0200_000c | ULITE_CONTROL | [RW] UART Configuration Register |\n| 0x0300_001c | SPI_DGIER | [RW] Device Global Interrupt Enable Register |\n| 0x0300_0020 | SPI_IPISR | [RW] IP Interrupt Status Register |\n| 0x0300_0028 | SPI_IPIER | [RW] IP Interrupt Enable Register |\n| 0x0300_0040 | SPI_SRR | [RW] Software Reset Register |\n| 0x0300_0060 | SPI_CR | [RW] SPI Control Register |\n| 0x0300_0064 | SPI_SR | [R] SPI Status Register |\n| 0x0300_0068 | SPI_DTR | [W] SPI Data Transmit Register |\n| 0x0300_006c | SPI_DRR | [R] SPI Data Receive Register |\n| 0x0300_0070 | SPI_SSR | [RW] SPI Slave Select Register |\n| 0x0400_0000 | GPIO_DIRECTION | [RW] Configuration Register |\n| 0x0400_0004 | GPIO_INPUT | [R] GPIO Input Status |\n| 0x0400_0008 | GPIO_OUTPUT | [RW] GPIO Output Control |\n| 0x0400_000c | GPIO_OUTPUT_SET | [W] GPIO Output Control Set Alias |\n| 0x0400_0010 | GPIO_OUTPUT_CLR | [W] GPIO Output Control Clr Alias |\n| 0x0400_0014 | GPIO_INT_MASK | [RW] GPIO Interrupt Enable Mask |\n| 0x0400_0018 | GPIO_INT_SET | [W] GPIO Interrupt Set |\n| 0x0400_001c | GPIO_INT_CLR | [W] GPIO Interrupt Clear |\n| 0x0400_0020 | GPIO_INT_STATUS | [R] GPIO Interrupt Raw Status |\n| 0x0400_0024 | GPIO_INT_LEVEL | [RW] GPIO Interrupt Level |\n| 0x0400_0028 | GPIO_INT_MODE | [RW] GPIO Interrupt Mode |\n\n### Peripheral Register Fields\n\n##### IRQ Register: IRQ_ISR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | STATUS | Pending interrupt (unmasked) bitmap. |\n\n##### IRQ Register: IRQ_IPR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | PENDING | Pending interrupts (masked) bitmap. |\n\n##### IRQ Register: IRQ_IER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | ENABLE | Interrupt enable mask. |\n\n##### IRQ Register: IRQ_IAR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | ACK | Bitmap of interrupts to acknowledge. |\n\n##### IRQ Register: IRQ_SIE\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | SET | Bitmap of interrupts to enable. |\n\n##### IRQ Register: IRQ_CIE\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | CLR | Bitmap of interrupts to disable. |\n\n##### IRQ Register: IRQ_IVR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VECTOR | Highest priority active interrupt number. |\n\n##### IRQ Register: IRQ_MER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | ME | Master Enable |\n\n##### Timer Register: TIMER_CTRLx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 1 | INTERRUPT | Interrupt enable. |\n| 2 | ENABLE | Timer enable. |\n\n##### Timer Register: TIMER_CMPx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Match value. |\n\n##### Timer Register: TIMER_VALx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | CURRENT | Current timer value. |\n\n##### UART Register: ULITE_RX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### UART Register: ULITE_TX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### UART Register: ULITE_STATUS\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 4 | IE | Interrupt enabled |\n| 3 | TXFULL | Transmit buffer full |\n| 2 | TXEMPTY | Transmit buffer empty |\n| 1 | RXFULL | Receive buffer full |\n| 0 | RXVALID | Receive buffer not empty |\n\n##### UART Register: ULITE_CONTROL\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 4 | IE | Interrupt enable |\n| 1 | RST_RX | Flush Rx Buffer |\n| 0 | RST_TX | Flush Tx Buffer |\n\n##### SPI Register: SPI_DGIER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31 | GIE | Global interrupt enable. |\n\n##### SPI Register: SPI_IPISR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 2 | TX_EMPTY | Tx FIFO empty interrupt status. |\n\n##### SPI Register: SPI_IPIER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 2 | TX_EMPTY | Tx FIFO interrupt enable. |\n\n##### SPI Register: SPI_SRR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | RESET | Software FIFO reset. |\n\n##### SPI Register: SPI_CR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | LOOP | Loopback enable (MOSI to MISO). |\n| 1 | SPE | SPI Enable. |\n| 2 | MASTER | Master mode (slave mode not currently supported). |\n| 3 | CPOL | Clock polarity. |\n| 4 | CPHA | Clock phase. |\n| 5 | TXFIFO_RST | Tx FIFO reset. |\n| 6 | RXFIFO_RST | Rx FIFO reset. |\n| 7 | MANUAL_SS | Manual chip select mode (auto mode not supported). |\n| 8 | TRANS_INHIBIT | Transfer inhibit. |\n| 9 | LSB_FIRST | Data LSB first (1) or MSB first (0). |\n\n##### SPI Register: SPI_SR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | RX_EMPTY | Rx FIFO empty. |\n| 1 | RX_FULL | Rx FIFO full. |\n| 2 | TX_EMPTY | Tx FIFO empty. |\n| 3 | TX_FULL | Tx FIFO full. |\n\n##### SPI Register: SPI_DTR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### SPI Register: SPI_DRR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### SPI Register: SPI_SSR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | VALUE | Chip select value |\n\n##### GPIO Register: GPIO_DIRECTION\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | OUTPUT | 0 = Input, 1 = Output |\n\n##### GPIO Register: GPIO_INPUT\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Raw input status |\n\n##### GPIO Register: GPIO_OUTPUT\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output value |\n\n##### GPIO Register: GPIO_OUTPUT_SET\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output mask - set for high |\n\n##### GPIO Register: GPIO_OUTPUT_CLR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output mask - set for low |\n\n##### GPIO Register: GPIO_INT_MASK\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ENABLE | GPIO Interrupt Enable Mask |\n\n##### GPIO Register: GPIO_INT_SET\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | SW_IRQ | Write 1 to assert an interrupt |\n\n##### GPIO Register: GPIO_INT_CLR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ACK | Write 1 to clear an interrupt |\n\n##### GPIO Register: GPIO_INT_STATUS\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | RAW | Set if interrupt active (regardless of INT_MASK) |\n\n##### GPIO Register: GPIO_INT_LEVEL\n\n| Bits | Name | Description    |\n| ---- | ---- | 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