{"id":19924281,"url":"https://github.com/ultraembedded/core_spiflash","last_synced_at":"2026-03-05T17:22:54.003Z","repository":{"id":81709571,"uuid":"182995708","full_name":"ultraembedded/core_spiflash","owner":"ultraembedded","description":"SPI-Flash XIP Interface (Verilog)","archived":false,"fork":false,"pushed_at":"2021-10-24T11:46:20.000Z","size":24,"stargazers_count":35,"open_issues_count":0,"forks_count":12,"subscribers_count":5,"default_branch":"master","last_synced_at":"2025-01-12T00:25:16.083Z","etag":null,"topics":["axi4","fpga","spi","spi-flash","verilog","xip"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-2.1","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-04-23T10:56:06.000Z","updated_at":"2024-09-26T08:47:02.000Z","dependencies_parsed_at":null,"dependency_job_id":"a7e6a472-c047-40a1-af8f-c53f2c97ba2c","html_url":"https://github.com/ultraembedded/core_spiflash","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_spiflash","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_spiflash/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_spiflash/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_spiflash/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_spiflash/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241351158,"owners_count":19948621,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["axi4","fpga","spi","spi-flash","verilog","xip"],"created_at":"2024-11-12T22:16:56.420Z","updated_at":"2026-03-05T17:22:53.968Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### SPI-Flash XIP Interface\n\nGithub:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/core_spiflash)\n\nThis component is a basic AXI4 to SPI Flash interface (1-bit read-only mode).\nUseful for executing bootloaders stored in FPGA configuration SPI PROMs.\n\n##### Interface\n\n| Name | Description   |\n| ---- | ------------- |\n| clk_i | Clock input |\n| rst_i | Async active high reset |\n| inport_* | AXI-4 slave interface |\n| spi_clk_o | SPI master clock output |\n| spi_mosi_o | SPI master data output |\n| spi_cs_o | SPI master chip select (active low) |\n| spi_miso_i | SPI master data input |\n\n\n##### Features\n* Single bit SPI Flash support (3 address cycles).\n* AXI4 slave supporting singles and bursts.\n* Supports SPI-Flash devices which support read page command (0x03).\n* Supports CPOL=0, CPHA=0 SPI (Mode 0) only.\n\n##### Testing\nVerified under simulation and tested on FPGA (XC7A35T with N25Q64A SPI-PROM).\n\n##### Configuration\n* parameter CLK_DIV - Clock divider ratio for clk_i -\u003e spi_clk_o (spi_clk = clk_i / (1 + CLK_DIV))\n* parameter tSLCH_CYCLES - Number of clk_i cycles from chip select to SPI transfer start\n* parameter tSLSL_CYCLES - Number of clk_i cycles chip select must remain in-active between transfers\n\n##### Area (Default config, Vivado, 7 series)\n- Slice LUTs:      341\n- Slice Registers: 162\n- BlockRAM:        0\n- DSP:             0\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_spiflash","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_spiflash","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_spiflash/lists"}