{"id":19924283,"url":"https://github.com/ultraembedded/core_ulpi_wrapper","last_synced_at":"2025-05-03T07:31:22.330Z","repository":{"id":50499486,"uuid":"261022329","full_name":"ultraembedded/core_ulpi_wrapper","owner":"ultraembedded","description":"ULPI Link Wrapper (USB Phy Interface)","archived":false,"fork":false,"pushed_at":"2020-05-03T21:38:34.000Z","size":30,"stargazers_count":25,"open_issues_count":3,"forks_count":9,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-04-07T13:11:13.067Z","etag":null,"topics":["fpga","ulpi","usb","usb-interface","verilog"],"latest_commit_sha":null,"homepage":null,"language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-05-03T21:15:43.000Z","updated_at":"2024-12-28T08:37:09.000Z","dependencies_parsed_at":"2022-09-13T04:41:13.607Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/core_ulpi_wrapper","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_ulpi_wrapper","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_ulpi_wrapper/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_ulpi_wrapper/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_ulpi_wrapper/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_ulpi_wrapper/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":252156891,"owners_count":21703370,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","ulpi","usb","usb-interface","verilog"],"created_at":"2024-11-12T22:16:56.527Z","updated_at":"2025-05-03T07:31:18.715Z","avatar_url":"https://github.com/ultraembedded.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"### ULPI Link Wrapper\n\nGithub:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/ulpi_wrapper)\n\nThis IP core converts from the UTMI interface to the reduced pin-count ULPI interface.\nThis enables interfacing from a standard USB SIE with UTMI interface to a USB 2.0 PHY.\n\nThis enables support of USB LS (1.5mbps), FS (12mbps) and HS (480mbps) transfers.\n\nThe design does not support low power mode.\n\nAll IOs are synchronous to the 60MHz ULPI clock input (sourced from the PHY), so care needs to be taken to configure the FPGA constraints to ensure the ULPI interface correctly meets timing.\n\n##### References\n\n* [UTMI+ Low Pin Interface (ULPI) Specification](https://www.sparkfun.com/datasheets/Components/SMD/ULPI_v1_1.pdf)\n* [SMSC USB3300 USB PHY Datasheet](http://ww1.microchip.com/downloads/en/DeviceDoc/3300db.pdf)\n\n##### Testing\n\nVerified under simulation and also on a Xilinx FPGA connected to a SMSC/Microchip USB3300 in device mode using the [USB3300 USB HS](http://www.waveshare.com/usb3300-usb-hs-board.htm) evaluation board.\n\nThe supplied testbench requires the SystemC libraries and Icarus Verilog, both of which are available for free.\n\n##### Size / Performance\n\nWith the current configuration...\n\n* This design consumes around 88 LUTs on a Xilinx Spartan 6 with IOB packing for the outputs.\n* There are around 90 flops in the design.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_ulpi_wrapper","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_ulpi_wrapper","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_ulpi_wrapper/lists"}