{"id":13996079,"url":"https://github.com/ultraembedded/core_uriscv","last_synced_at":"2026-02-14T12:03:19.170Z","repository":{"id":81709585,"uuid":"366142849","full_name":"ultraembedded/core_uriscv","owner":"ultraembedded","description":"Another tiny RISC-V implementation","archived":false,"fork":false,"pushed_at":"2021-07-19T21:00:00.000Z","size":67,"stargazers_count":59,"open_issues_count":1,"forks_count":15,"subscribers_count":4,"default_branch":"main","last_synced_at":"2025-10-03T12:35:07.997Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2021-05-10T18:40:27.000Z","updated_at":"2025-09-03T22:52:18.000Z","dependencies_parsed_at":null,"dependency_job_id":"cf1f5843-7250-4ae1-b02f-d69297624318","html_url":"https://github.com/ultraembedded/core_uriscv","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_uriscv","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_uriscv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_uriscv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_uriscv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_uriscv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_uriscv/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_uriscv/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29443468,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-14T10:51:12.367Z","status":"ssl_error","status_checked_at":"2026-02-14T10:50:52.088Z","response_time":53,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-09T14:03:48.112Z","updated_at":"2026-02-14T12:03:19.152Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":["Verilog"],"sub_categories":[],"readme":"### uriscv - Another tiny RISC-V implementation\n\nGithub:   [https://github.com/ultraembedded/core_uriscv](https://github.com/ultraembedded/core_uriscv)\n\nSimple, small, multi-cycle 32-bit RISC-V CPU implementation.  \nMost instructions take 2 cycles, apart from load/stores which take 4+ cycles (depending on memory latency), and division which can take up-to 34 cycles.\n\n## Features\n* 32-bit RISC-V ISA CPU core.\n* Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).\n* Implements base ISA spec v2.1 and parts of the privileged ISA spec v1.11.\n* Supports machine mode privilege level only.\n* Configurable support for exceptions, interrupts, timers, multiplication, division and error traps.\n* Verified using random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).\n* Synthesizable Verilog 2001, Verilator and FPGA friendly.\n* Coremark:  **1.48 CoreMark/MHz** (with HW mul/div)\n* Dhrystone: **0.58 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration / with HW mul/div)\n\n**For my higher performance pipelined cores, see here:**\n* Coremark:  **2.94CM/MHZ** - [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)\n* Coremark:  **4.1CM/MHz** - [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)\n\n## Getting Started\n\n#### Cloning\n\nTo clone this project and its dependencies;\n\n```\ngit clone https://github.com/ultraembedded/core_uriscv.git\n\n```\n\n#### Running Helloworld\n\nTo run a simple test image on the core RTL using Icarus Verilog;\n\n```\n# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)\nsudo apt-get install iverilog\n\n# [or] Install Icarus Verilog (Redhat / Centos)\n#sudo yum install iverilog\n\n# Run a simple test image (test.elf)\ncd tb/tb_core_icarus\nmake\n```\n\nThe expected output is;\n```\nStarting bench\nVCD info: dumpfile waveform.vcd opened for output.\n\nTest:\n1. Initialised data\n2. Multiply\n3. Divide\n4. Shift left\n5. Shift right\n6. Shift right arithmetic\n7. Signed comparision\n8. Word access\n9. Byte access\n10. Comparision\n```\n#### Configuration\n\n| Param Name                | Valid Range  | Description                                                 |\n| ------------------------- |:------------:| ------------------------------------------------------------|\n| SUPPORT_MUL               | 1/0          | Enable multiplication instructions.                         |\n| SUPPORT_DIV               | 1/0          | Enable division instructions.                               |\n| SUPPORT_CSR               | 1/0          | Global enable for CSR/trap/interrupt handling.              |\n| SUPPORT_TRAP_LSU_ALIGN    | 1/0          | Enable unaligned memory load / store exception.             |\n| SUPPORT_MTVEC             | 1/0          | Configurable exception entry address.                       |\n| SUPPORT_MTVAL             | 1/0          | Support MTVAL CSR (holds bad addr / opcode).                |\n| SUPPORT_MIP_MIE           | 1/0          | Support MIE and MIP CSR registers.                          |\n| SUPPORT_MSCRATCH          | 1/0          | Support MSCRATCH CSR registers (SW read/write).             |\n| SUPPORT_MCYCLE            | 1/0          | Support cycle counter / rdtime.                             |\n| SUPPORT_MTIMECMP          | 1/0          | Non-std - support timer compare interrupt.                  |\n| SUPPORT_TRAP_INVALID_OPC  | 1/0          | Fault on invalid opcodes (enable SW emulation).             |\n| SUPPORT_BRAM_REGFILE      | 1/0          | FPGA BlockRAM friendly reg file (inst take 1 cycle longer). |\n| ISR_VECTOR                | 'h0-FFFFFFFF | ISR addr = reset_vector + ISR_VECTOR (SUPPORT_MTVEC = 0).   |\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_uriscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_uriscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_uriscv/lists"}