{"id":19924276,"url":"https://github.com/ultraembedded/core_usb_bridge","last_synced_at":"2026-01-31T20:03:08.199Z","repository":{"id":81709587,"uuid":"197964589","full_name":"ultraembedded/core_usb_bridge","owner":"ultraembedded","description":"USB -\u003e AXI Debug Bridge","archived":false,"fork":false,"pushed_at":"2021-06-05T15:49:06.000Z","size":23,"stargazers_count":39,"open_issues_count":0,"forks_count":11,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-06-21T21:46:01.424Z","etag":null,"topics":["axi4-lite","fpga","usb","usb-cdc","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-2.1","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-07-20T17:55:08.000Z","updated_at":"2025-05-23T18:06:47.000Z","dependencies_parsed_at":null,"dependency_job_id":"24d02562-b7e2-4614-9da1-3f693eaad20b","html_url":"https://github.com/ultraembedded/core_usb_bridge","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_usb_bridge","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_bridge","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_bridge/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_bridge/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_bridge/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_usb_bridge/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_bridge/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28952578,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-31T18:30:42.805Z","status":"ssl_error","status_checked_at":"2026-01-31T18:30:19.593Z","response_time":128,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["axi4-lite","fpga","usb","usb-cdc","verilog"],"created_at":"2024-11-12T22:16:56.318Z","updated_at":"2026-01-31T20:03:08.168Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### USB -\u003e AXI Debug Bridge\n\nGithub:   [http://github.com/ultraembedded/core_usb_bridge](https://github.com/ultraembedded/core_usb_bridge)\n\nThis component is a USB (CDC-ACM / USB Serial) to AXI4-Lite bus master bridge.  \nThis IP enumerates as a full speed (12Mbit/s) USB device which can then be used to read / write to memories / peripherals in your FPGA based SoC.\n\nThe PHY / transceiver are built in requiring no additional external hardware other than a USB port connected to the FPGA I/Os.\n\n#### Cloning\n\nThis repo contains submodules, and to clone them run the following command;\n\n```\ngit clone --recursive https://github.com/ultraembedded/core_usb_bridge.git\n\n```\n\n####  Design Files\n```\nusb_bridge_top.v\n├── usb_bridge\n│   └── src_v\n│       ├── usb_bridge_fifo.v\n│       └── usb_bridge.v\n├── usb_cdc\n│   └── src_v\n│       ├── usb_cdc_core.v\n│       ├── usb_desc_rom.v\n│       ├── usbf_crc16.v\n│       ├── usbf_defs.v\n│       ├── usbf_device_core.v\n│       ├── usbf_sie_ep.v\n│       ├── usbf_sie_rx.v\n│       └── usbf_sie_tx.v\n└── usb_fs_phy\n    └── src_v\n        ├── usb_fs_phy.v\n        └── usb_transceiver.v\n```\n\n#### Configuration / Requirements\n* Top: usb_bridge_top\n* Clock: clk_i - 48MHz\n* Reset: rst_i - Asynchronous, active high\n* VID/PID can be changed in usb_desc_rom.v\n\n#### Hardware\n\nConnection from your FPGA I/Os can be made simply using a breakout board;\n* [https://www.sparkfun.com/products/12035](https://www.sparkfun.com/products/12035)\n\nIn order to enumerate as a USB FS device, there must be a pull-up on the D+ pin (but not on the D- pin).  \nThis can be achieved using the internal pull-ups on some FPGAs (though how reliable this is remains to be seen).\n\nExample constraints (Xilinx Vivado);\n```\nset_property -dict { PACKAGE_PIN N4    IOSTANDARD LVCMOS33 } [get_ports { usb_dp_io }]; # USB D+\nset_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { usb_dn_io }]; # USB D-\nset_property PULLUP TRUE [get_ports usb_dp_io]\n```\n\nFor Xilinx FPGAs, pad pull-ups should be disabled before configuration is completed (PUDC_B).\n\n#### Software\nIncluded python based utils provide peek and poke access, plus binary load / dump support.\n\nExamples:\n```\n# Read a memory location (0x0)\n./sw/peek.py -d /dev/ttyACM0 -a 0x0\n\n# Write a memory word (0x0 = 0x12345678)\n./sw/poke.py -d /dev/ttyACM0 -a 0x0 -v 0x12345678\n``` \n\n#### References\n* [USB Full Speed PHY](https://github.com/ultraembedded/core_usb_fs_phy)\n* [USB CDC Device](https://github.com/ultraembedded/core_usb_cdc)","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_bridge","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_usb_bridge","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_bridge/lists"}