{"id":19924280,"url":"https://github.com/ultraembedded/core_usb_cdc","last_synced_at":"2026-02-14T12:01:37.600Z","repository":{"id":51323626,"uuid":"197954777","full_name":"ultraembedded/core_usb_cdc","owner":"ultraembedded","description":"Basic USB-CDC device core (Verilog)","archived":false,"fork":false,"pushed_at":"2021-05-15T10:18:15.000Z","size":39,"stargazers_count":80,"open_issues_count":2,"forks_count":18,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-09-18T14:14:39.048Z","etag":null,"topics":["fpga","usb","usb-cdc","usb-device","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-2.1","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-07-20T16:22:16.000Z","updated_at":"2025-09-02T11:08:41.000Z","dependencies_parsed_at":"2022-08-30T08:30:55.196Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/core_usb_cdc","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_usb_cdc","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_cdc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_cdc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_cdc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_cdc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_usb_cdc/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_cdc/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29443468,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-14T10:51:12.367Z","status":"ssl_error","status_checked_at":"2026-02-14T10:50:52.088Z","response_time":53,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","usb","usb-cdc","usb-device","verilog"],"created_at":"2024-11-12T22:16:56.414Z","updated_at":"2026-02-14T12:01:37.577Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### USB CDC Device\n\nGithub:   [http://github.com/ultraembedded/core_usb_cdc](https://github.com/ultraembedded/core_usb_cdc)\n\nThis component is a simple USB Peripheral Interface (Device) implementation which enumerates as either a high-speed (480Mbit/s) or full-speed (12Mbit/s) CDC-ACM device.\n\nThis IP has a simple FIFO interface (valid, data, accept) for input and output data, and an UTMI interface for connection to a USB PHY.\n\n##### Features\n* High or Full speed USB CDC device.\n* Enumeration in hardware - no SW intervention required.\n* UTMI PHY interface (see my UTMI to ULPI Conversion wrapper project to allow connection to a ULPI PHY e.g. USB3300)\n* Simple 8-bit data input / output interface with handshaking (compliant with a 8-bit wide AXI4-Stream interface).\n\n##### Configuration / Requirements (Full Speed (12Mbit/s))\n* Top: usb_cdc_core\n* Clock: clk_i - 48MHz or 60MHz\n* Reset: rst_i - Asynchronous, active high\n* VID/PID can be changed in usb_desc_rom.v\n* Param: USB_SPEED_HS = \"False\"\n\n##### Configuration / Requirements (High Speed (480Mbit/s))\n* Top: usb_cdc_core\n* Clock: clk_i - 60MHz\n* Reset: rst_i - Asynchronous, active high\n* VID/PID can be changed in usb_desc_rom.v\n* Param: USB_SPEED_HS = \"True\"\n\n##### Limitations\n* Really basic USB-CDC class device implementation, will ignore encap, line state and line coding change requests!\n* USB suspend/resume will not work correctly.\n\n##### Testing\nVerified under simulation then tested on FPGA against Linux, Windows and MAC OS-X.\n\n##### FuseSoC support\n\nUSB CDC can be linted with verilator or made into a GDSII with OpenLANE\nusing FuseSoC. Quick FuseSoC instructions\n\n```\n#install FuseSoC\npip3 install fusesoc\n\n#Create and enter a new workspace\nmkdir workspace \u0026\u0026 cd workspace\n\n#Register usb cdc as a library in the workspace\nfusesoc library add usb_cdc /path/to/core_usb_cdc\n#...if repo is available locally or...\nfusesoc library add usb_cdc https://github.com/ultraembedded/core_usb_cdc\n#...to get the upstream repo\n\n#To run linter\nfusesoc run --target=lint ultraembedded:core:usb_cdc\n#List all targets\nfusesoc core show ultraembedded:core:usb_cdc\n\n#Create a GDSII using a dockerized OpenLANE\n#Requires the sky130 PDK and an Edalize launcher script\nexport PDK_ROOT=/path/to/sky130_pdk\nexport EDALIZE_LAUNCHER=/path/to/openlane_runner.py\nfusesoc run --target=sky130 ultraembedded:core:usb_cdc\n```\n\n##### References\n* [USB 2.0 Specification](https://usb.org/developers/docs/usb20_docs)\n* [UTMI Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf)\n* [ULPI Specification](https://www.sparkfun.com/datasheets/Components/SMD/ULPI_v1_1.pdf)\n* [USB Made Simple](http://www.usbmadesimple.co.uk/)\n* [UTMI to ULPI Conversion](https://github.com/ultraembedded/cores/tree/master/ulpi_wrapper)\n* [USB Full Speed PHY](https://github.com/ultraembedded/core_usb_fs_phy)","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_cdc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_usb_cdc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_cdc/lists"}