{"id":19924279,"url":"https://github.com/ultraembedded/core_usb_fs_phy","last_synced_at":"2026-03-08T14:37:30.360Z","repository":{"id":81709598,"uuid":"197960813","full_name":"ultraembedded/core_usb_fs_phy","owner":"ultraembedded","description":"USB Full Speed PHY","archived":false,"fork":false,"pushed_at":"2020-05-03T19:47:47.000Z","size":18,"stargazers_count":41,"open_issues_count":1,"forks_count":6,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-03-01T10:25:11.298Z","etag":null,"topics":["fpga","usb","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-2.1","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-07-20T17:17:31.000Z","updated_at":"2025-02-26T10:43:50.000Z","dependencies_parsed_at":null,"dependency_job_id":"44458bb8-7a98-4d1b-a119-1f20dd8564b4","html_url":"https://github.com/ultraembedded/core_usb_fs_phy","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_usb_fs_phy","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_fs_phy","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_fs_phy/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_fs_phy/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_fs_phy/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_usb_fs_phy/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_fs_phy/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30261857,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-08T08:59:44.879Z","status":"ssl_error","status_checked_at":"2026-03-08T08:58:02.867Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","usb","verilog"],"created_at":"2024-11-12T22:16:56.398Z","updated_at":"2026-03-08T14:37:30.345Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"### USB Full Speed PHY\n\nGithub:   [http://github.com/ultraembedded/core_usb_fs_phy](https://github.com/ultraembedded/core_usb_fs_phy)\n\nThis component implements the low level USB1.1 / FS / 12Mbit/s USB signalling (SOP,DATA,EOP) with the required bitstuffing.\n\n##### Features\n* UTMI PHY interface.\n* Connection to a transceiver (e.g. USB1T11A) or can drive the FPGA pins directly as USB D+/D-.\n\n##### Configuration / Requirements\n* Top: usb_fs_phy\n* Clock: clk_i - 48MHz\n* Reset: rst_i - Asynchronous, active high\n\n##### Testing\nTested with various FPGA + USB based projects.\n\n##### FPGA Transceiver\nTo avoid external components, you can drive the USB D+/D- pins directly from the FPGA fabric.\nThe USB1.1 bit rate is low enough (12MHz) for this to be not too problematic with short cables!\n\n```\nmodule usb_fs_phy_wrapper\n(\n     input           clk_i\n    ,input           rst_i\n\n    ,input  [  7:0]  utmi_data_out_i\n    ,input           utmi_txvalid_i\n    ,input  [  1:0]  utmi_op_mode_i\n    ,input  [  1:0]  utmi_xcvrselect_i\n    ,input           utmi_termselect_i\n    ,input           utmi_dppulldown_i\n    ,input           utmi_dmpulldown_i\n    ,output [  7:0]  utmi_data_in_o\n    ,output          utmi_txready_o\n    ,output          utmi_rxvalid_o\n    ,output          utmi_rxactive_o\n    ,output          utmi_rxerror_o\n    ,output [  1:0]  utmi_linestate_o\n\n    // USB D+ / D-\n    ,inout          usb_dp_io\n    ,inout          usb_dn_io\n);\n\nwire           usb_pads_rx_rcv_w;\nwire           usb_pads_rx_dn_w;\nwire           usb_pads_rx_dp_w;\nwire           usb_pads_tx_dn_w;\nwire           usb_pads_tx_dp_w;\nwire           usb_pads_tx_oen_w;\n\nusb_transceiver u_usb_xcvr\n(\n    // Inputs\n     .usb_phy_tx_dp_i(usb_pads_tx_dp_w)\n    ,.usb_phy_tx_dn_i(usb_pads_tx_dn_w)\n    ,.usb_phy_tx_oen_i(usb_pads_tx_oen_w)\n    ,.mode_i(1'b1)\n\n    // Outputs\n    ,.usb_dp_io(usb_dp_io)\n    ,.usb_dn_io(usb_dn_io)\n    ,.usb_phy_rx_rcv_o(usb_pads_rx_rcv_w)\n    ,.usb_phy_rx_dp_o(usb_pads_rx_dp_w)\n    ,.usb_phy_rx_dn_o(usb_pads_rx_dn_w)\n);\n\nusb_fs_phy u_usb_phy\n(\n    // Inputs\n     .clk_i(clk_i)\n    ,.rst_i(rst_i)\n    ,.utmi_data_out_i(utmi_data_out_i)\n    ,.utmi_txvalid_i(utmi_txvalid_i)\n    ,.utmi_op_mode_i(utmi_op_mode_i)\n    ,.utmi_xcvrselect_i(utmi_xcvrselect_i)\n    ,.utmi_termselect_i(utmi_termselect_i)\n    ,.utmi_dppulldown_i(utmi_dppulldown_i)\n    ,.utmi_dmpulldown_i(utmi_dmpulldown_i)\n    ,.usb_rx_rcv_i(usb_pads_rx_rcv_w)\n    ,.usb_rx_dp_i(usb_pads_rx_dp_w)\n    ,.usb_rx_dn_i(usb_pads_rx_dn_w)\n    ,.usb_reset_assert_i(1'b0)\n\n    // Outputs\n    ,.utmi_data_in_o(utmi_data_in_o)\n    ,.utmi_txready_o(utmi_txready_o)\n    ,.utmi_rxvalid_o(utmi_rxvalid_o)\n    ,.utmi_rxactive_o(utmi_rxactive_o)\n    ,.utmi_rxerror_o(utmi_rxerror_o)\n    ,.utmi_linestate_o(utmi_linestate_o)\n    ,.usb_tx_dp_o(usb_pads_tx_dp_w)\n    ,.usb_tx_dn_o(usb_pads_tx_dn_w)\n    ,.usb_tx_oen_o(usb_pads_tx_oen_w)\n    ,.usb_reset_detect_o()\n    ,.usb_en_o()\n);\n\nendmodule\n```\n\nExample contraints;\n```\nset_property -dict { PACKAGE_PIN N4    IOSTANDARD LVCMOS33 } [get_ports { usb_dp_io }];\nset_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { usb_dn_io }];\nset_property PULLUP TRUE [get_ports usb_dp_io]\n```\n\n##### References\n* [UTMI Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf)\n* [USB1T11A](http://www.mouser.com/ds/2/149/fairchild%20semiconductor_usb1t11a-320893.pdf)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_fs_phy","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_usb_fs_phy","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_fs_phy/lists"}