{"id":19924259,"url":"https://github.com/ultraembedded/core_usb_uart","last_synced_at":"2026-03-06T01:01:59.443Z","repository":{"id":46556108,"uuid":"259013153","full_name":"ultraembedded/core_usb_uart","owner":"ultraembedded","description":"USB serial device (CDC-ACM)","archived":false,"fork":false,"pushed_at":"2020-06-28T12:12:26.000Z","size":27,"stargazers_count":37,"open_issues_count":1,"forks_count":10,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-03-01T10:25:19.883Z","etag":null,"topics":["fpga","serial-port","uart","usb-cdc","usb-device","usb-serial","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-04-26T11:27:42.000Z","updated_at":"2024-12-24T10:18:09.000Z","dependencies_parsed_at":"2022-09-12T01:01:23.112Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/core_usb_uart","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/core_usb_uart","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_uart","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_uart/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_uart/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_uart/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/core_usb_uart/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Fcore_usb_uart/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30156847,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-05T22:39:40.138Z","status":"ssl_error","status_checked_at":"2026-03-05T22:39:24.771Z","response_time":93,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","serial-port","uart","usb-cdc","usb-device","usb-serial","verilog"],"created_at":"2024-11-12T22:16:52.700Z","updated_at":"2026-03-06T01:01:59.424Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","readme":"### USB Serial Port Device (USB-CDC)\n\nGithub:   [https://github.com/ultraembedded/core_usb_uart](https://github.com/ultraembedded/core_usb_uart)\n\nThis component is a simple USB Peripheral Interface (Device) implementation which enumerates as either a high-speed (480Mbit/s) or full-speed (12Mbit/s) CDC-ACM device.\n\nThis IP acts as a USB to serial port (UART) converter which can be used to add a UART to a FPGA which has a ULPI interface.\n\n##### Features\n* High or Full speed USB CDC device.\n* Enumeration in hardware - no SW intervention required.\n* ULPI interface (suitable for connection to a ULPI PHY - e.g. Microchip USB3300)\n* Fixed baud rate (param) Rx, Tx pins.\n\n##### Example instantiation (Xilinx)\n```\nmodule usb_serial\n//-----------------------------------------------------------------\n// Params\n//-----------------------------------------------------------------\n#(\n    parameter BAUDRATE         = 1000000\n)\n//-----------------------------------------------------------------\n// Ports\n//-----------------------------------------------------------------\n(\n      output          uart_rx_o\n    , input           uart_tx_i\n\n    // ULPI Interface\n    , output          ulpi_reset_o\n    , inout [7:0]     ulpi_data_io\n    , output          ulpi_stp_o\n    , input           ulpi_nxt_i\n    , input           ulpi_dir_i\n    , input           ulpi_clk60_i\n);\n\n// USB clock / reset\nwire usb_clk_w;\nwire usb_rst_w;\n\nwire clk_bufg_w;\nIBUF u_ibuf ( .I(ulpi_clk60_i), .O(clk_bufg_w) );\nBUFG u_bufg ( .I(clk_bufg_w),   .O(usb_clk_w) );\n\nreg [3:0] count_q = 4'b0;\nreg       rst_q   = 1'b1;\n\nalways @(posedge usb_clk_w) \nif (count_q != 4'hF)\n    count_q \u003c= count_q + 4'd1;\nelse\n    rst_q \u003c= 1'b0;\n\nassign usb_rst_w = rst_q;\n\n// ULPI Buffers\nwire [7:0] ulpi_out_w;\nwire [7:0] ulpi_in_w;\nwire       ulpi_stp_w;\n\ngenvar i;\ngenerate  \nfor (i=0; i \u003c 8; i=i+1)  \nbegin: gen_buf\n    IOBUF \n    #(\n        .DRIVE(12),\n        .IOSTANDARD(\"DEFAULT\"),\n        .SLEW(\"FAST\")\n    )\n    IOBUF_inst\n    (\n        .T(ulpi_dir_i),\n        .I(ulpi_out_w[i]),\n        .O(ulpi_in_w[i]),\n        .IO(ulpi_data_io[i])\n    );\nend  \nendgenerate  \n\nOBUF \n#(\n    .DRIVE(12),\n    .IOSTANDARD(\"DEFAULT\"),\n    .SLEW(\"FAST\")\n)\nOBUF_stp\n(\n    .I(ulpi_stp_w),\n    .O(ulpi_stp_o)\n);\n\n// USB Core\nusb_cdc_top\n#( .BAUDRATE(BAUDRATE) )\nu_usb\n(\n     .clk_i(usb_clk_w)\n    ,.rst_i(usb_rst_w)\n\n    // ULPI\n    ,.ulpi_data_out_i(ulpi_in_w)\n    ,.ulpi_dir_i(ulpi_dir_i)\n    ,.ulpi_nxt_i(ulpi_nxt_i)\n    ,.ulpi_data_in_o(ulpi_out_w)\n    ,.ulpi_stp_o(ulpi_stp_w)\n\n    ,.tx_i(uart_tx_i)\n    ,.rx_o(uart_rx_o)\n);\n\nassign ulpi_reset_o = 1'b0;\n\nendmodule\n```\n\n##### Limitations\n* Really basic USB-CDC class device implementation, will ignore encap, line state and line coding change requests!\n* USB suspend/resume will not work correctly.\n\n##### Testing\nVerified under simulation then tested on FPGA against Linux, Windows and MAC OS-X.\n\n##### References\n* [USB 2.0 Specification](https://usb.org/developers/docs/usb20_docs)\n* [ULPI Specification](https://www.sparkfun.com/datasheets/Components/SMD/ULPI_v1_1.pdf)\n* [USB Made Simple](http://www.usbmadesimple.co.uk/)\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_uart","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fcore_usb_uart","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fcore_usb_uart/lists"}