{"id":19924274,"url":"https://github.com/ultraembedded/fpgamp","last_synced_at":"2025-04-13T06:42:09.405Z","repository":{"id":81709636,"uuid":"295548279","full_name":"ultraembedded/FPGAmp","owner":"ultraembedded","description":"720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)","archived":false,"fork":false,"pushed_at":"2020-11-21T12:02:41.000Z","size":13102,"stargazers_count":275,"open_issues_count":0,"forks_count":43,"subscribers_count":17,"default_branch":"master","last_synced_at":"2025-03-24T11:50:17.571Z","etag":null,"topics":["artix-7","fpga","fpga-media-player","hd-video","hdmi","ir-codes","jpeg-decoder","mjpeg","motion-jpeg","risc-v","rtos","sd-card","vga"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-09-14T21:59:47.000Z","updated_at":"2025-03-05T12:56:50.000Z","dependencies_parsed_at":"2023-10-31T06:00:22.925Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/FPGAmp","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2FFPGAmp","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2FFPGAmp/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2FFPGAmp/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2FFPGAmp/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/FPGAmp/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248675440,"owners_count":21143763,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["artix-7","fpga","fpga-media-player","hd-video","hdmi","ir-codes","jpeg-decoder","mjpeg","motion-jpeg","risc-v","rtos","sd-card","vga"],"created_at":"2024-11-12T22:16:56.050Z","updated_at":"2025-04-13T06:42:09.386Z","avatar_url":"https://github.com/ultraembedded.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA Media Player\n\nThis project is a FPGA based media player which is capable of playing [Motion JPEG](https://en.wikipedia.org/wiki/Motion_JPEG) encoded video over HDMI or VGA on commonly available FPGA boards.\n\n![](docs/demo.png)\n\n## Features\n* 1280x720 [720p50 / 'standard HD'] 25fps video (also supports 24fps)\n* 44.1KHz stereo audio (I2S or SPDIF)\n* Hardware accelerated JPEG decoding\n* SD/MMC card interface (FAT16/32 support)\n* MP3 playback (SW codec)\n* JPEG stills display\n* IR remote control\n\n## Rationale\n*Why?* For the fun of it!  \nThis project was an interesting test case for a number of my open-source digital IPs (RISC-V CPU, audio+video controllers), and also brings together various SW projects that I had written in years past (RTOS, FAT32 library).\n\n## Supported Hardware\n* [Digilent Arty A7](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) + [PMOD I2S2](https://reference.digilentinc.com/reference/pmod/pmodi2s2/start) + [PMOD MicroSD](https://reference.digilentinc.com/reference/pmod/pmodmicrosd/start) + [PMOD VGA](https://reference.digilentinc.com/reference/pmod/pmodvga/start) or PMOD2HDMI Breakout Cable + IR receiver\n\n![ArtyA7](docs/arty.png)\n\n## Cloning\n\nThis repo contains submodules.  \nMake sure to clone them all with the following command;\n\n```\ngit clone --recursive https://github.com/ultraembedded/FPGAmp.git\n\n```\n\n## Block Diagram\n![Block Diagram](docs/block_diagram.png)\n\n## Project Files\n\nThe FPGA gateware for this project is constructed from various sub-projects;\n* [CPU - RISC-V](https://github.com/ultraembedded/riscv)\n* [Peripherals](https://github.com/ultraembedded/core_soc)\n* [UART -\u003e AXI Debug Bridge](https://github.com/ultraembedded/core_dbg_bridge)\n* [SD/MMC interface](https://github.com/ultraembedded/core_mmc)\n* [JPEG decoder](https://github.com/ultraembedded/core_jpeg_decoder)\n* [Audio controller](https://github.com/ultraembedded/core_audio)\n* [DVI framebuffer](https://github.com/ultraembedded/core_dvi_framebuffer)\n\nOn the firmware side, this project uses;\n* [Custom RTOS](https://github.com/ultraembedded/librtos)\n* [FAT32 Library](https://github.com/ultraembedded/fat_io_lib)\n* [MP3 decoder](https://github.com/ultraembedded/libhelix-mp3)\n* [LVGL User Interface](https://github.com/lvgl/lvgl)\n\n## Getting Started\n\nThe firmware needs to be built with the 32-bit RISC-V (RVIM) GCC;\n```\n# 1. Build firmware\ncd firmware/app\nmake\n\n# 2. Copy firmware/app/build.riscv.boot/boot.bin to a FAT32 SD card\n```\n\nThe bootROM in the FPGA fabric will automatically load 'boot.bin' from the SD card root directory.  \n**NOTE**: The SD card must be formatted as FAT16 or FAT32 and not EXFAT!\n\nDebug messages will be comming out of the ArtyA7 USB-UART @ 1M baud (8N1).\n\n## IR Remote\nThe project can be controlled via an IR remote (NEC protocol, currently).  \nThe IR codes are device-specific but can be changed here;\n```\n// firmware/app/ir_decode.h\n#define IR_CMD_RIGHT    0x20df609f\n#define IR_CMD_LEFT     0x20dfe01f\n#define IR_CMD_DOWN     0x20df827d\n#define IR_CMD_UP       0x20df02fd\n#define IR_CMD_BACK     0x20df14eb\n```\n\nHandily, the UART outputs any received IR codes so it is relatively straight forward to tune the controls to a new remote.\n\n![IR Connection](docs/ir_conn.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Ffpgamp","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Ffpgamp","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Ffpgamp/lists"}