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open-logic-bit\n*Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.*\n\nGithub: [https://github.com/ultraembedded/openlogicbit](https://github.com/ultraembedded/openlogicbit)\n\n![Demo-uart](docs/pulseview_uart.png)\n\n## Aims\nA logic analyzer project which aims to provide reliable, high speed (100MHz+), large capture depth, open-source gateware that can be used on a FPGA development board you already own, or as replacement gateware for commercial logic analysers that do not work with open-source tools such as [sigrok](https://sigrok.org/).\n\nThis project aims to support FPGA boards with 10's MBs of capture memory (such as DDR3), which also have high-speed USB interfaces from which to download the captured data.\n\nThere are a number of other open-source logic analyzer projects, but these mostly focus on using limited internal FPGA memories (embedded block RAMs), and low-performance host interfaces (UART).\n\n## Features\n* 16, 24, 32 input channels supported.\n* Run-length encoded (RLE) compression to extend the sample buffer depth.\n* Support for boards with large memories (DDR, SDRAM).\n* Up to 32 triggers supporting edge, level, value match modes.\n* Support for boards with FTDI sync FIFO mode support (FT232H, FT2232H).\n* Support for external clock sources.\n* Continuous or one-shot capture modes.\n* libsigrok support available (enabling support for Sigrok, Pulseview).\n\n*A screenshot of Sigrok capturing a SPDIF signal at 100MHz with open-logic-bit running on a Digilent Digital Discovery;*\n![Demo-spdif](docs/pulseview_spdif.png)\n\n## Supported Boards\n* [Digilent Digital Discovery](https://reference.digilentinc.com/test-and-measurement/digital-discovery/start)\n* More to come...\n\n## Software\nCompatible with Sigrok (via libsigrok), based on the following fork;\n* [https://github.com/ultraembedded/libsigrok](https://github.com/ultraembedded/libsigrok)\n\n*open-logic-bit also contains a built in test mode;*\n![Demo-counter](docs/pulseview_counter.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fopenlogicbit","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fopenlogicbit","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fopenlogicbit/lists"}