{"id":13649358,"url":"https://github.com/ultraembedded/riscv","last_synced_at":"2026-01-26T21:50:22.396Z","repository":{"id":20239271,"uuid":"23511343","full_name":"ultraembedded/riscv","owner":"ultraembedded","description":"RISC-V CPU Core (RV32IM)","archived":false,"fork":false,"pushed_at":"2021-09-18T17:52:55.000Z","size":5529,"stargazers_count":1398,"open_issues_count":15,"forks_count":251,"subscribers_count":53,"default_branch":"master","last_synced_at":"2025-03-22T23:45:02.645Z","etag":null,"topics":["asic","cpu","fpga","pipeline-processor","risc-v","riscv-linux","rv32i","rv32im","verification","verilator","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ultraembedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-08-31T10:38:22.000Z","updated_at":"2025-03-20T12:25:31.000Z","dependencies_parsed_at":"2022-07-12T15:17:37.978Z","dependency_job_id":null,"html_url":"https://github.com/ultraembedded/riscv","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ultraembedded/riscv","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ultraembedded","download_url":"https://codeload.github.com/ultraembedded/riscv/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28789100,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-26T21:49:50.245Z","status":"ssl_error","status_checked_at":"2026-01-26T21:48:29.455Z","response_time":59,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","cpu","fpga","pipeline-processor","risc-v","riscv-linux","rv32i","rv32im","verification","verilator","verilog"],"created_at":"2024-08-02T01:04:57.886Z","updated_at":"2026-01-26T21:50:22.380Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","readme":"# RISC-V Core\n\nGithub: [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)\n\nA 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.  \nThis core has been tested against a co-simulation model and exercised on FPGA.\n\n**For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here;**\n[http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)\n\n## Overview\n![](doc/overview.png)\n\n## Features\n* 32-bit RISC-V ISA CPU core.\n* Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).\n* Supports user, supervisor and machine mode privilege levels.\n* Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.\n* Implements base ISA spec [v2.1](https://github.com/ultraembedded/riscv/tree/master/doc/riscv_isa_spec.pdf) and privileged ISA spec [v1.11](https://github.com/ultraembedded/riscv/tree/master/doc/riscv_privileged_spec.pdf).\n* Verified using [Google's RISCV-DV](https://github.com/google/riscv-dv) random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).\n* Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.\n* Configurable number of pipeline stages and result forwarding options.\n* Synthesizable Verilog 2001, Verilator and FPGA friendly.\n* Coremark:  **2.94 CoreMark/MHz**\n* Dhrystone: **1.25 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)\n* Want higher performance (**4.1CM/MHz** / **1.9DMIPS/MHz**) - see [my improved core](http://github.com/ultraembedded/biriscv).\n\n#### Configuration\n\n| Param Name                | Valid Range          | Description                                   |\n| ------------------------- |:--------------------:| ----------------------------------------------|\n| SUPPORT_SUPER             | 1/0                  | Enable supervisor / user privilege levels.    |\n| SUPPORT_MMU               | 1/0                  | Enable basic memory management unit.          |\n| SUPPORT_MULDIV            | 1/0                  | Enable HW multiply / divide (RV-M).           |\n| SUPPORT_LOAD_BYPASS       | 1/0                  | Support load result bypass paths.             |\n| SUPPORT_MUL_BYPASS        | 1/0                  | Support multiply result bypass paths.         |\n| SUPPORT_REGFILE_XILINX    | 1/0                  | Support Xilinx optimised register file.       |\n| EXTRA_DECODE_STAGE        | 1/0                  | Extra decode pipe stage for improved timing.  |\n| MEM_CACHE_ADDR_MIN        | 32'h0 - 32'hffffffff | Lowest cacheable memory address.              |\n| MEM_CACHE_ADDR_MAX        | 32'h0 - 32'hffffffff | Highest cacheable memory address.             |\n\n## Directories\n\n| Name                | Contents                                            |\n| ------------------- | --------------------------------------------------- |\n| core/riscv          | RISC-V pipelined RV32IM CPU core (Verilog)          |\n| isa_sim             | Instruction set simulator (C)                       |\n| top_tcm_axi/src_v   | Example instance with 64KB DP-RAM \u0026 AXI Interfaces  |\n| top_tcm_axi/tb      | System-C testbench for the core                     |\n| top_cache_axi/src_v | Example instance with instruction and data caches.  |\n| top_cache_axi/tb    | System-C testbench for the core                     |\n\n## Example Core Instance (with TCM memory)\n\nThe top (top_tcm_axi/src_v/riscv_tcm_top.v) contains;\n* Instances one of the above cores, adding RAM and standard bus interfaces.\n* 64KB dual ported RAM for (I/D code and data).\n* AXI4 slave port for loading the RAM, DMA access, etc (including support for burst access).\n* AXI4-Lite master port for CPU access to peripherals.\n* Separate reset for CPU core to dual ported RAM / AXI interface (to allow program code to be loaded prior to CPU reset de-assertion).\n\n### Memory Map\n\n| Range                     | Description                                         |\n| ------------------------- | --------------------------------------------------- |\n| 0x0000_0000 - 0x0000_ffff | 64KB TCM Memory                                     |\n| 0x0000_2000               | Boot address (configurable, see RISCV_BOOT_ADDRESS) |\n| 0x8000_0000 - 0xffff_ffff | Peripheral address space (from AXI4-L port)         |\n\n### Interfaces\n\n| Name         | Description                                                           |\n| ------------ | --------------------------------------------------------------------- |\n| clk_i        | Clock input                                                           |\n| rst_i        | Async reset, active-high. Reset memory / AXI interface.               |\n| rst_cpu_i    | Async reset, active-high. Reset CPU core (excluding AXI / memory).    |\n| axi_t_*      | AXI4 slave interface for access to 64KB TCM memory.                   |\n| axi_i_*      | AXI4-Lite master interface for CPU access to peripherals.             |\n| intr_i       | Active high interrupt input (for connection external int controller). |\n\n### Testbench\n\nA basic System-C / Verilator based testbench for the core is provided.\n\nDependencies;\n* gcc\n* make\n* libelf\n* System-C (specify path using SYSTEMC_HOME)\n* Verilator (specify path using VERILATOR_SRC)\n\nTo build the testbench;\n```\ncd top_tcm_axi/tb\nmake\n````\n\nTo run the provided test executable;\n```\ncd top_tcm_axi/tb\nmake run\n````\n\n## Example Core Instance (with caches)\n\nThe top (top_cache_axi/src_v/riscv_top.v) contains;\n* Instances one of the above cores, adding RAM and standard bus interfaces.\n* 16KB 2-way set associative instruction cache\n* 16KB 2-way set associative data cache with write-back and allocate on write.\n* 2 x AXI4 master port for CPU access to instruction / data / peripherals.\n\n### Interfaces\n\n| Name           | Description                                                           |\n| -------------- | --------------------------------------------------------------------- |\n| clk_i          | Clock input                                                           |\n| rst_i          | Async reset, active-high. Reset memory / AXI interface.               |\n| axi_i_*        | AXI4 master interface for CPU access to instruction memory.           |\n| axi_d_*        | AXI4 master interface for CPU access to data / peripheral memories.   |\n| intr_i         | Active high interrupt input (for connection external int controller). |\n| reset_vector_i | Boot vector.                                                          |\n\n## Execution Example\n![](doc/core_exec.png)\n","funding_links":[],"categories":["Verilog","CPU RISC-V","Applications"],"sub_categories":["网络服务_其他"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Friscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Friscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Friscv/lists"}