{"id":19924254,"url":"https://github.com/ultraembedded/riscv_soc","last_synced_at":"2025-07-29T06:08:28.162Z","repository":{"id":81709924,"uuid":"175998038","full_name":"ultraembedded/riscv_soc","owner":"ultraembedded","description":"Basic RISC-V Test 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RISC-V Test SoC\n\nGithub: http://github.com/ultraembedded/riscv_soc\n\nA basic RISC-V test SoC with Timer, UART, SPI and GPIO peripherals...\n\n## Cloning\n```\n# Clone repository and submodules\ngit clone https://github.com/ultraembedded/riscv_soc.git --recursive\n```\n\n## Directories\n\n| Name                | Contents                                            |\n| ------------------- | --------------------------------------------------- |\n| core                | RISC-V core (http://github.com/ultraembedded/riscv) |\n| fpga/arty           | Digilent Artix-7 Arty FPGA Dev Board project        |\n| soc                 | Verilog for peripherals, interconnect, etc          |\n| tb                  | System-C testbench for the project                  |\n\n## Features\n\nThe top (riscv_soc in riscv_soc.v) contains;\n* RISC-V core (RV32IM instructions supported).\n* 16KB (8KB x 2-way) instruction cache.\n* Timer, UART, SPI and interrupt controller peripherals.\n* AXI4-Lite slave port for external bus master/debug access to peripherals / main memory.\n* AXI4 master port for access to main memory, e.g. SDRAM (external to the design).\n\n## Interfaces\n\n| Name           | Description                                                           |\n| -------------- | --------------------------------------------------------------------- |\n| clk_i          | Clock input                                                           |\n| rst_i          | Async reset, active-high. Reset SoC (excluding CPU core).             |\n| rst_cpu_i      | Async reset, active-high. Reset CPU core.                             |\n| reset_vector_i | Initial boot address.                                                 |\n| inport_*       | AXI4-Lite slave interface for access to SoC / memory.                 |\n| mem_*          | AXI4 master interface to main memory.                                 |\n| spi_*          | SPI interface                                                         |\n| gpio_*         | GPIO interface                                                        |\n| uart_rxd_o     | UART Tx (connect to remote receiver)                                  |\n| uart_txd_i     | UART Rx (connect to remote transmitter)                               |\n\n## Testbench\n\nA basic System-C / Verilator based testbench for the design is provided.\n\nDependancies;\n* gcc\n* make\n* libelf\n* System-C (specify path using SYSTEMC_HOME)\n* Verilator (specify path using VERILATOR_SRC)\n\nTo build the testbench;\n```\ncd tb\nmake \n````\n\nTo run the provided test executable;\n```\ncd tb\nmake run\n````\n\n## FPGA\n\nThis project is ready to run on the 'Digilent Artix-7 Arty' FPGA dev board;\n\n![](doc/arty.png)\n\nA pre-cooked bitstream for this board is located in 'fpga/arty/top.bit'.\n\nThe test project for FPGA uses the [UART to AXI dbg bridge](https://github.com/ultraembedded/cores/tree/master/dbg_bridge) to allow code to be loaded into DDR prior to de-asserting the CPU's reset.\n\nThe 'rv32imsu' core (as used in the provided bitstream) is capable of booting Linux;\n\n```\ncd fpga/arty\n\n# Load bitstream onto target\nvivado -mode tcl -source program.tcl\n\n# Load test app into DDR and release reset (change ttyUSB2 as appropriate)\n./run.py -d /dev/ttyUSB2 -f ../../images/linux_riscv_soc.elf \n\nELF: Loading 0x80000000 - size 7KB\n |XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX| 100.0% \nELF: Loading 0x80400000 - size 5368KB\n |XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX| 100.0% \nELF: Loading 0x81f00000 - size 2KB\n |XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX| 100.0% \n\n[Console]: Enter UART mode\nBooting...\nOF: fdt: Ignoring memory range 0x80000000 - 0x80400000\nLinux version 4.19.0-29706-g1479c35-dirty (build@vm) (gcc version 7.2.0 (GCC)) #531 Sat Mar 16 22:07:04 GMT 2019\nbootconsole [early0] enabled\ninitrd not found or empty - disabling initrd\nZone ranges:\n  Normal   [mem 0x0000000080400000-0x0000081effffffff]\nMovable zone start for each node\nEarly memory node ranges\n  node   0: [mem 0x0000000080400000-0x0000000081efffff]\nInitmem setup node 0 [mem 0x0000000080400000-0x0000000081efffff]\nOn node 0 totalpages: 6912\n  Normal zone: 54 pages used for memmap\n  Normal zone: 0 pages reserved\n  Normal zone: 6912 pages, LIFO batch:0\nelf_hwcap is 0x1101\npcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768\npcpu-alloc: [0] 0 \nBuilt 1 zonelists, mobility grouping on.  Total pages: 6858\nKernel command line: console=ttyUL0,1000000 debug\nDentry cache hash table entries: 4096 (order: 2, 16384 bytes)\nInode-cache hash table entries: 2048 (order: 1, 8192 bytes)\nSorting __ex_table...\nMemory: 21992K/27648K available (3664K kernel code, 138K rwdata, 547K rodata, 792K init, 220K bss, 5656K reserved, 0K cma-reserved)\nSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\nNR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0\nirq-xilinx: /soc/interrupt-controller@90000000: num_irq=9, edge=0x100\nclocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 76450417870 ns\nConsole: colour dummy device 80x25\nCalibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=100000)\npid_max: default: 32768 minimum: 301\nMount-cache hash table entries: 1024 (order: 0, 4096 bytes)\nMountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)\ndevtmpfs: initialized\nrandom: get_random_u32 called from bucket_table_alloc.isra.7+0xa0/0x208 with crng_init=0\nclocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns\nfutex hash table entries: 256 (order: -1, 3072 bytes)\nNET: Registered protocol family 16\nrandom: fast init done\nclocksource: Switched to clocksource timer\nNET: Registered protocol family 2\ntcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes)\nTCP established hash table entries: 1024 (order: 0, 4096 bytes)\nTCP bind hash table entries: 1024 (order: 0, 4096 bytes)\nTCP: Hash tables configured (established 1024 bind 1024)\nUDP hash table entries: 256 (order: 0, 4096 bytes)\nUDP-Lite hash table entries: 256 (order: 0, 4096 bytes)\nNET: Registered protocol family 1\nworkingset: timestamp_bits=30 max_order=13 bucket_order=0\nNET: Registered protocol family 38\nBlock layer SCSI generic (bsg) driver version 0.4 loaded (major 254)\nio scheduler noop registered\nio scheduler deadline registered\nio scheduler cfq registered (default)\nio scheduler mq-deadline registered\nio scheduler kyber registered\n92000000.serial: ttyUL0 at MMIO 0x92000000 (irq = 2, base_baud = 0) is a uartlite\nconsole [ttyUL0] enabled\nconsole [ttyUL0] enabled\nbootconsole [early0] disabled\nbootconsole [early0] disabled\nloop: module loaded\nNET: Registered protocol family 10\nSegment Routing with IPv6\nsit: IPv6, IPv4 and MPLS over IPv4 tunneling driver\nNET: Registered protocol family 17\nFreeing unused kernel memory: 792K\nThis architecture does not have kernel memory protection.\nRun /init as init process\ninit started: BusyBox v1.29.3 (2018-11-13 23:09:48 GMT)\n\nPlease press Enter to activate this console. \n\nBusyBox v1.29.3 (2018-11-13 23:09:48 GMT) built-in shell (ash)\n\n# ls\nbin   dev   etc   init  lib   mnt   proc  sbin  sys   test\n# \n```\n\n## Size\n\n### SoC + Small Core (core/rv32i_spartan6)\n\n| Xilinx Vivado (for XC7)    | Used |\n|----------------------------|------|\n| Slice LUTs                 | 3654 |\n| Slice Registers            | 1468 |\n\n### SoC + Larger Core (core/rv32imsu)\n\n| Xilinx Vivado (for XC7)    | Used |\n|----------------------------|------|\n| Slice LUTs                 | 7046 |\n| Slice Registers            | 3170 |\n\n\n## Memory Map\n\n| Range                     | Description                                         |\n| ------------------------- | --------------------------------------------------- |\n| 0x8000_0000 - 0x8fff_ffff | Main memory (external to the design)                |\n| 0x9000_0000 - 0x90ff_ffff | Peripheral - IRQ controller                         |\n| 0x9100_0000 - 0x91ff_ffff | Peripheral - Timer                                  |\n| 0x9200_0000 - 0x92ff_ffff | Peripheral - UART                                   |\n| 0x9300_0000 - 0x93ff_ffff | Peripheral - SPI                                    |\n| 0x9400_0000 - 0x94ff_ffff | Peripheral - GPIO                                   |\n\n## Interrupt Sources\n\n| Index  | Source                      |\n| -------| --------------------------- |\n|   0    | Peripheral - Timer          |\n|   1    | Peripheral - UART           |\n|   2    | Peripheral - SPI            |\n|   3    | Peripheral - GPIO           |\n\n## Peripheral Register Map\n\n| Offset | Name | Description   |\n| ------ | ---- | ------------- |\n| 0x9000_0000 | IRQ_ISR | [RW] Interrupt Status Register |\n| 0x9000_0004 | IRQ_IPR | [R] Interrupt Pending Register |\n| 0x9000_0008 | IRQ_IER | [RW] Interrupt Enable Register |\n| 0x9000_000c | IRQ_IAR | [W] Interrupt Acknowledge Register |\n| 0x9000_0010 | IRQ_SIE | [W] Set Interrupt Enable bits |\n| 0x9000_0014 | IRQ_CIE | [W] Clear Interrupt Enable bits |\n| 0x9000_0018 | IRQ_IVR | [RW] Interrupt Vector Register |\n| 0x9000_001c | IRQ_MER | [RW] Master Enable Register |\n| 0x9100_0008 | TIMER_CTRL0 | [RW] Control |\n| 0x9100_000c | TIMER_CMP0 | [RW] Compare value (interrupt on match) |\n| 0x9100_0010 | TIMER_VAL0 | [RW] Current Value |\n| 0x9100_0014 | TIMER_CTRL1 | [RW] Control |\n| 0x9100_0018 | TIMER_CMP1 | [RW] Compare value (interrupt on match) |\n| 0x9100_001c | TIMER_VAL1 | [RW] Current Value |\n| 0x9200_0000 | ULITE_RX | [R] UART Data Register |\n| 0x9200_0004 | ULITE_TX | [W] UART Data Register |\n| 0x9200_0008 | ULITE_STATUS | [R] UART Status Register |\n| 0x9200_000c | ULITE_CONTROL | [RW] UART Configuration Register |\n| 0x9300_001c | SPI_DGIER | [RW] Device Global Interrupt Enable Register |\n| 0x9300_0020 | SPI_IPISR | [RW] IP Interrupt Status Register |\n| 0x9300_0028 | SPI_IPIER | [RW] IP Interrupt Enable Register |\n| 0x9300_0040 | SPI_SRR | [RW] Software Reset Register |\n| 0x9300_0060 | SPI_CR | [RW] SPI Control Register |\n| 0x9300_0064 | SPI_SR | [R] SPI Status Register |\n| 0x9300_0068 | SPI_DTR | [W] SPI Data Transmit Register |\n| 0x9300_006c | SPI_DRR | [R] SPI Data Receive Register |\n| 0x9300_0070 | SPI_SSR | [RW] SPI Slave Select Register |\n| 0x9400_0000 | GPIO_DIRECTION | [RW] Configuration Register |\n| 0x9400_0004 | GPIO_INPUT | [R] GPIO Input Status |\n| 0x9400_0008 | GPIO_OUTPUT | [RW] GPIO Output Control |\n| 0x9400_000c | GPIO_OUTPUT_SET | [W] GPIO Output Control Set Alias |\n| 0x9400_0010 | GPIO_OUTPUT_CLR | [W] GPIO Output Control Clr Alias |\n| 0x9400_0014 | GPIO_INT_MASK | [RW] GPIO Interrupt Enable Mask |\n| 0x9400_0018 | GPIO_INT_SET | [W] GPIO Interrupt Set |\n| 0x9400_001c | GPIO_INT_CLR | [W] GPIO Interrupt Clear |\n| 0x9400_0020 | GPIO_INT_STATUS | [R] GPIO Interrupt Raw Status |\n| 0x9400_0024 | GPIO_INT_LEVEL | [RW] GPIO Interrupt Level |\n| 0x9400_0028 | GPIO_INT_MODE | [RW] GPIO Interrupt Mode |\n\n### Peripheral Register Fields\n\n##### IRQ Register: IRQ_ISR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | STATUS | Pending interrupt (unmasked) bitmap. |\n\n##### IRQ Register: IRQ_IPR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | PENDING | Pending interrupts (masked) bitmap. |\n\n##### IRQ Register: IRQ_IER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | ENABLE | Interrupt enable mask. |\n\n##### IRQ Register: IRQ_IAR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | ACK | Bitmap of interrupts to acknowledge. |\n\n##### IRQ Register: IRQ_SIE\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | SET | Bitmap of interrupts to enable. |\n\n##### IRQ Register: IRQ_CIE\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 3:0 | CLR | Bitmap of interrupts to disable. |\n\n##### IRQ Register: IRQ_IVR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VECTOR | Highest priority active interrupt number. |\n\n##### IRQ Register: IRQ_MER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | ME | Master Enable |\n\n##### Timer Register: TIMER_CTRLx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 1 | INTERRUPT | Interrupt enable. |\n| 2 | ENABLE | Timer enable. |\n\n##### Timer Register: TIMER_CMPx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Match value. |\n\n##### Timer Register: TIMER_VALx\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | CURRENT | Current timer value. |\n\n##### UART Register: ULITE_RX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### UART Register: ULITE_TX\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### UART Register: ULITE_STATUS\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 4 | IE | Interrupt enabled |\n| 3 | TXFULL | Transmit buffer full |\n| 2 | TXEMPTY | Transmit buffer empty |\n| 1 | RXFULL | Receive buffer full |\n| 0 | RXVALID | Receive buffer not empty |\n\n##### UART Register: ULITE_CONTROL\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 4 | IE | Interrupt enable |\n| 1 | RST_RX | Flush Rx Buffer |\n| 0 | RST_TX | Flush Tx Buffer |\n\n##### SPI Register: SPI_DGIER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31 | GIE | Global interrupt enable. |\n\n##### SPI Register: SPI_IPISR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 2 | TX_EMPTY | Tx FIFO empty interrupt status. |\n\n##### SPI Register: SPI_IPIER\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 2 | TX_EMPTY | Tx FIFO interrupt enable. |\n\n##### SPI Register: SPI_SRR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | RESET | Software FIFO reset. |\n\n##### SPI Register: SPI_CR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | LOOP | Loopback enable (MOSI to MISO). |\n| 1 | SPE | SPI Enable. |\n| 2 | MASTER | Master mode (slave mode not currently supported). |\n| 3 | CPOL | Clock polarity. |\n| 4 | CPHA | Clock phase. |\n| 5 | TXFIFO_RST | Tx FIFO reset. |\n| 6 | RXFIFO_RST | Rx FIFO reset. |\n| 7 | MANUAL_SS | Manual chip select mode (auto mode not supported). |\n| 8 | TRANS_INHIBIT | Transfer inhibit. |\n| 9 | LSB_FIRST | Data LSB first (1) or MSB first (0). |\n\n##### SPI Register: SPI_SR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | RX_EMPTY | Rx FIFO empty. |\n| 1 | RX_FULL | Rx FIFO full. |\n| 2 | TX_EMPTY | Tx FIFO empty. |\n| 3 | TX_FULL | Tx FIFO full. |\n\n##### SPI Register: SPI_DTR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### SPI Register: SPI_DRR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 7:0 | DATA | Date byte |\n\n##### SPI Register: SPI_SSR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 0 | VALUE | Chip select value |\n\n##### GPIO Register: GPIO_DIRECTION\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | OUTPUT | 0 = Input, 1 = Output |\n\n##### GPIO Register: GPIO_INPUT\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | VALUE | Raw input status |\n\n##### GPIO Register: GPIO_OUTPUT\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output value |\n\n##### GPIO Register: GPIO_OUTPUT_SET\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output mask - set for high |\n\n##### GPIO Register: GPIO_OUTPUT_CLR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | DATA | GPIO output mask - set for low |\n\n##### GPIO Register: GPIO_INT_MASK\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ENABLE | GPIO Interrupt Enable Mask |\n\n##### GPIO Register: GPIO_INT_SET\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | SW_IRQ | Write 1 to assert an interrupt |\n\n##### GPIO Register: GPIO_INT_CLR\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ACK | Write 1 to clear an interrupt |\n\n##### GPIO Register: GPIO_INT_STATUS\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | RAW | Set if interrupt active (regardless of INT_MASK) |\n\n##### GPIO Register: GPIO_INT_LEVEL\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | ACTIVE_HIGH | GPIO Interrupt Level - 1 = active high / rising edge, 0 = active low / falling edge |\n\n##### GPIO Register: GPIO_INT_MODE\n\n| Bits | Name | Description    |\n| ---- | ---- | -------------- |\n| 31:0 | EDGE | GPIO Interrupt Mode - 1 = edge triggered, 0 = level |\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Friscv_soc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Friscv_soc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Friscv_soc/lists"}