{"id":19924253,"url":"https://github.com/ultraembedded/xc6_bus_pirate","last_synced_at":"2026-03-04T16:02:13.308Z","repository":{"id":81709959,"uuid":"275933376","full_name":"ultraembedded/xc6_bus_pirate","owner":"ultraembedded","description":"XC6 Bus Pirate (FPGA based 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unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-12T22:16:51.321Z","updated_at":"2026-03-04T16:02:13.275Z","avatar_url":"https://github.com/ultraembedded.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# XC6 Bus Pirate (FPGA based)\n\n**This is a re-release of an old project from 2013/2014 but with recently updated RTL.**\n\nThe 'Bus Pirate' was an open-source universal bus interface module produced by [Dangerous Prototypes](http://dangerousprototypes.com/docs/Bus_Pirate).  \nBack in 2013/2014, I decided to do a FPGA based version using the Xilinx Spartan-6 with USB implemented in the FPGA fabric.  \nHere was the [Hack A Day](https://hackaday.com/?s=fpga+bus+pirate) write-up.\n\n![XC6BP](docs/xc6bp.jpg)\n\nAt the time, RISC-V had yet to reach popularity so I implemented an OpenRISC based CPU along with a SW based USB stack implementing USB-CDC (virtual serial port) protocol.  \nMore recently, RISC-V has become the defacto open-source CPU ISA and is hugely more popular than OpenRISC ever was.\n\nI now have a number of well verified RISC-V implementations;\n* [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)\n* [https://github.com/ultraembedded/riscv](https://github.com/ultraembedded/riscv)\n\nI also now have an HW based USB -\u003e AXI Debug Bridge;\n* [https://github.com/ultraembedded/core_usb_bridge](https://github.com/ultraembedded/core_usb_bridge)\n\nThis is more reliable than the SW implementation and frees up blockRAM for more useful things.\n\nThis release makes use of new IP designs  (RISC-V CPU, HW only USB core) on an old HW project.\n\nTo clone this project and its dependencies;\n\n```\ngit clone --recursive https://github.com/ultraembedded/xc6_bus_pirate.git\n```\n\n## Hardware\nThe HW design is very basic and was based around the hobbyist friendly Spartan6 TQG144 part (LX9).  \n*This part is not 5V friendly, and the board has no over-voltage protection on its I/Os...*\n\n**Components**\n* Xilinx Spartan 6 LX9\n* USB1T11A - USB full-speed transceiver\n* 8 GPIO (compatible with Olimex UEXT pinout)\n* FTDI compatible serial port header\n* 4Mbit SPI-Flash (FPGA configuration + application code)\n* 128KB SPI/SQI SRAM\n* 6MHz oscillator\n* 3v3 LDO\n\nThe design fits in the original 'Bus Pirate' case (DP6037).\n\n![PCB](docs/pcb.png)\n\n\n## IP Components\n\nMost of the IP cores used in this project are designed by myself and available as easy to follow open-source Verilog modules.\n\n| Name                   | Description                                                 | Provider |\n| ---------------------- | ------------------------------------------------------------| -------- |\n| riscv_tcm_top          | [32-bit RISC-V CPU - RV32I](https://github.com/ultraembedded/riscv) | - |\n| usb_bridge             | [USB Debug Bridge](https://github.com/ultraembedded/core_usb_bridge) | - |\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fxc6_bus_pirate","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fultraembedded%2Fxc6_bus_pirate","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fultraembedded%2Fxc6_bus_pirate/lists"}