{"id":13645077,"url":"https://github.com/umd-memsys/DRAMSim2","last_synced_at":"2025-04-21T13:31:45.403Z","repository":{"id":47125094,"uuid":"649650","full_name":"umd-memsys/DRAMSim2","owner":"umd-memsys","description":"DRAMSim2: A cycle accurate DRAM simulator","archived":false,"fork":false,"pushed_at":"2020-11-11T20:47:28.000Z","size":8442,"stargazers_count":249,"open_issues_count":32,"forks_count":151,"subscribers_count":31,"default_branch":"master","last_synced_at":"2024-08-02T01:24:29.629Z","etag":null,"topics":["c-plus-plus","computer-architecture","dram","simulator"],"latest_commit_sha":null,"homepage":"http://www.ece.umd.edu/~blj/papers/cal10-1.pdf","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/umd-memsys.png","metadata":{"files":{"readme":"README","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2010-05-06T03:32:10.000Z","updated_at":"2024-07-28T06:15:45.000Z","dependencies_parsed_at":"2022-09-01T20:34:43.309Z","dependency_job_id":null,"html_url":"https://github.com/umd-memsys/DRAMSim2","commit_stats":null,"previous_names":[],"tags_count":4,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMSim2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMSim2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMSim2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMSim2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/umd-memsys","download_url":"https://codeload.github.com/umd-memsys/DRAMSim2/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223867781,"owners_count":17216956,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c-plus-plus","computer-architecture","dram","simulator"],"created_at":"2024-08-02T01:02:25.819Z","updated_at":"2024-11-09T18:30:16.461Z","avatar_url":"https://github.com/umd-memsys.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"DRAMSim\n\n1. About DRAMSim ---------------------------------------------------------\n\tDRAMSim is a cycle accurate model of a DRAM memory controller, the DRAM\n\tmodules which comprise system storage, and the bus by which they\n\tcommunicate. All major components in a modern memory system are modeled\n\tas their own respective objects within the source, including: ranks,\n\tbanks, command queue, the memory controller, etc.\n\n\tWe also added support and config files for STT-MRAM, \n\tyou can run the simulations the same way as DRAM. \n\tRefer Asifuzzaman, K., etc. Enabling a reliable STT-MRAM main memory simulation (MEMSYS2017)\n\tfor more info about STT-MRAM.\n\n\tThe overarching goal is to have a simulator that is extremely small,\n\tportable, and accurate. The simulator core has a well-defined interface\n\twhich allows it to be CPU simulator agnostic and should be easily\n\tmodifiably to work with any simulator.  This core has no external run\n\ttime or build time dependencies and has been tested with g++ on Linux\n\tas well as g++ on Cygwin on Windows.  \n\n2. Building DRAMSim ---------------------------------------------------------\n\n\tTo build an optimized DRAMSim simply type\n\n\t$ make\n\n\tFor a debug build which contains debugging symbols and verbose output, run:\n\n\t$ make DEBUG=1\n\n\tthis will compile an executable called DRAMSim which can run a\n\ttrace-based simulation. \n\n\tTo build the DRAMSim library, type: \n\n\t$ make libdramsim.so \n\t\n\n3. Running DRAMSim -----------------------------------------------------------\n\t\n\tFirst, run the preprocessor on the gzipped traces:\n\n\tcd traces\n\t./traceParse.py k6_aoe_02_short.trc.gz\n\n\tThen go back to the DRAMSim directory and run the trace based simulator:\n\tcd ..\n\t./DRAMSim -t traces/k6_aoe_02_short.trc -s system.ini -d ini/DDR3_micron_64M_8B_x4_sg15.ini -c 10000\n\n4. DRAMSim Output -------------------------------------------------------------\n\nThe verbosity of the DRAMSim can be customized in the ini file by turning the\nvarious debug flags on or off in the ini file. \n\nBelow, we have provided a detailed explanation of the simulator output.  With\nall DEBUG flags enabled, the following output is displayed for each cycle\nexecuted.  \n\n   NOTE : BP = Bus Packet\n\t  T  = Transaction\n\t  MC = MemoryController\n\t  R# = Rank (index #)\n\n-------------------------------------------------------------\n ----------------- Memory System Update ------------------\n ---------- Memory Controller Update Starting ------------ [8]\n -- R0 Receiving On Bus    : BP [ACT] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]\n -- MC Issuing On Data Bus    : BP [DATA] pa[0x7edc7e0] r[0] b[2] row[2029] col[799] data[0]=\n ++ Adding Read energy to total energy\n -- MC Issuing On Command Bus : BP [READ_P] pa[0x5dec7f8] r[1] b[3] row[1502] col[799]\n== New Transaction - Mapping Address [0x5dec800]\n  Rank : 0\n  Bank : 0\n  Row  : 1502\n  Col  : 800\n ++ Adding IDD3N to total energy [from rank 0]\n ++ Adding IDD3N to total energy [from rank 1]\n== Printing transaction queue\n  8]T [Read] [0x45bbfa4]\n  9]T [Write] [0x55fbfa0] [5439E]\n  10]T [Write] [0x55fbfa8] [1111]\n== Printing bank states (According to MC)\n[idle] [idle] [2029] [1502] \n[idle] [idle] [1502] [1502] \n\n== Printing Per Rank, Per Bank Queue\n = Rank 0\n    Bank 0   size : 2\n       0]BP [ACT] pa[0x5dec800] r[0] b[0] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec800] r[0] b[0] row[1502] col[800]\n    Bank 1   size : 2\n       0]BP [ACT] pa[0x5dec810] r[0] b[1] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec810] r[0] b[1] row[1502] col[800]\n    Bank 2   size : 2\n       0]BP [ACT] pa[0x5dec7e0] r[0] b[2] row[1502] col[799]\n       1]BP [READ_P] pa[0x5dec7e0] r[0] b[2] row[1502] col[799]\n    Bank 3   size : 1\n       0]BP [READ_P] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]\n = Rank 1\n    Bank 0   size : 2\n       0]BP [ACT] pa[0x5dec808] r[1] b[0] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec808] r[1] b[0] row[1502] col[800]\n    Bank 1   size : 2\n       0]BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec818] r[1] b[1] row[1502] col[800]\n    Bank 2   size : 1\n       0]BP [READ_P] pa[0x5dec7e8] r[1] b[2] row[1502] col[799]\n    Bank 3   size : 0\n-----------------------------------------------------\n\n\n\n  Anything sent on the bus is encapsulated in an BusPacket (BP) object. \n  When printing, they display the following information:\n\t\t\t BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]\n  The information displayed  is (in order):command type, physical address,\n  rank #, bank#, row #, and column #.\n\n  Lines beginning with \" -- \" indicate bus traffic, ie, \n     -- R0 Receiving On Bus       : BP [ACT] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]\n     -- MC Issuing On Data Bus    : BP [DATA] pa[0x7edc7e0] r[0] b[2] row[2029] col[799] data[0]=\n     -- MC Issuing On Command Bus : BP [READ_P] pa[0x5dec7f8] r[1] b[3] row[1502] col[799]\n  Sender and receiver are indicated and the packet being sent is detailed.\n\n\n  Lines beginning with \" ++ \" indicate power calculations, ie, \n\t\t ++ Adding Read energy to total energy\n \t\t ++ Adding IDD3N to total energy [from rank 0]\n \t\t ++ Adding IDD3N to total energy [from rank 1]\n  The state of the system and the actions taken determine which current\n  draw is used.  for further detail about each current, see micron data-\n  sheet.\n\n\tIf a pending transaction is in the transaction queue, it will\n  be printed, as seen below:\n\t\t == Printing transaction queue\t\t\n  \t \t\t1]T [Read] [0x45bbfa4]\n  \t\t\t2]T [Write] [0x55fbfa0] [5439E]\n \t\t\t  3]T [Write] [0x55fbfa8] [1111]\n  Currently, at the start of every cycle, the head of the transaction\n  queue is removed, broken up into DRAM commands and placed in the\n  appropriate command queues.  To do this, an address mapping scheme\n  is applied to the transaction's physical address, the output of \n  which is seen below:\n\t\t\t== New Transaction - Mapping Address [0x5dec800]\n  \t\t\t Rank : 0\n\t\t\t\t Bank : 0\n\t\t\t\t Row  : 1502\n\t\t\t\t Col  : 800\n\n  If there are pending commands in the command queue, they will be\n  printed.  The output is dependent on the designated structure for\n  the command queue.  For example, per-rank/per-bank queues are \n  shown below:\n   = Rank 1\n    Bank 0   size : 2\n       0]BP [ACT] pa[0x5dec808] r[1] b[0] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec808] r[1] b[0] row[1502] col[800]\n    Bank 1   size : 2\n       0]BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]\n       1]BP [READ_P] pa[0x5dec818] r[1] b[1] row[1502] col[800]\n    Bank 2   size : 1\n       0]BP [READ_P] pa[0x5dec7e8] r[1] b[2] row[1502] col[799]\n    Bank 3   size : 0\n\n  The state of each bank in the system is also displayed:\n    == Printing bank states (According to MC)\n    [idle] [idle] [2029] [1502] \n    [idle] [idle] [1502] [1502] \n  Banks can be in many states, including idle, row active (shown\n  with the row that is active), refreshing, or precharging.  These\n  states will update based on the commands being sent by the \n  controller.  \n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fumd-memsys%2FDRAMSim2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fumd-memsys%2FDRAMSim2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fumd-memsys%2FDRAMSim2/lists"}