{"id":13645115,"url":"https://github.com/umd-memsys/DRAMsim3","last_synced_at":"2025-04-21T13:31:45.079Z","repository":{"id":41273013,"uuid":"129306792","full_name":"umd-memsys/DRAMsim3","owner":"umd-memsys","description":"DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator","archived":false,"fork":false,"pushed_at":"2024-08-03T03:24:21.000Z","size":3285,"stargazers_count":310,"open_issues_count":37,"forks_count":143,"subscribers_count":13,"default_branch":"master","last_synced_at":"2024-11-09T18:41:35.260Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/umd-memsys.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-04-12T20:19:12.000Z","updated_at":"2024-10-29T06:25:41.000Z","dependencies_parsed_at":"2022-08-10T01:43:27.159Z","dependency_job_id":"5007fde0-244a-4674-a69f-cd911aa21479","html_url":"https://github.com/umd-memsys/DRAMsim3","commit_stats":{"total_commits":524,"total_committers":9,"mean_commits":58.22222222222222,"dds":0.3225190839694656,"last_synced_commit":"29817593b3389f1337235d63cac515024ab8fd6e"},"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMsim3","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMsim3/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMsim3/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/umd-memsys%2FDRAMsim3/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/umd-memsys","download_url":"https://codeload.github.com/umd-memsys/DRAMsim3/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250064681,"owners_count":21368948,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:02:27.610Z","updated_at":"2025-04-21T13:31:44.532Z","avatar_url":"https://github.com/umd-memsys.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"[![Build Status](https://travis-ci.com/umd-memsys/DRAMsim3.svg?branch=master)](https://travis-ci.com/umd-memsys/DRAMsim3)\n\n# About DRAMsim3\n\nDRAMsim3 models the timing paramaters and memory controller behavior for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected oriented model that includes a parameterized DRAM bank model, DRAM controllers, command queues and system-level interfaces to interact with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed to be accurate, portable and parallel.\n    \nIf you use this simulator in your work, please consider cite:\n\n[1] S. Li, Z. Yang, D. Reddy, A. Srivastava and B. Jacob, \"DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator,\" in IEEE Computer Architecture Letters. [Link](https://ieeexplore.ieee.org/document/8999595)\n\nSee [Related Work](#related-work) for more work done with this simulator.\n\n\n## Building and running the simulator\n\nThis simulator by default uses a CMake based build system.\nThe advantage in using a CMake based build system is portability and dependency management.\nWe require CMake 3.0+ to build this simulator.\nIf `cmake-3.0` is not available,\nwe also supply a Makefile to build the most basic version of the simulator.\n\n### Building\n\nDoing out of source builds with CMake is recommended to avoid the build files cluttering the main directory.\n\n```bash\n# cmake out of source build\nmkdir build\ncd build\ncmake ..\n\n# Build dramsim3 library and executables\nmake -j4\n\n# Alternatively, build with thermal module enabled\ncmake .. -DTHERMAL=1\n\n```\n\nThe build process creates `dramsim3main` and executables in the `build` directory.\nBy default, it also creates `libdramsim3.so` shared library in the project root directory.\n\n### Running\n\n```bash\n# help\n./build/dramsim3main -h\n\n# Running random stream with a config file\n./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini --stream random -c 100000 \n\n# Running a trace file\n./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100000 -t sample_trace.txt\n\n# Running with gem5\n--mem-type=dramsim3 --dramsim3-ini=configs/DDR4_4Gb_x4_2133.ini\n\n```\n\nThe output can be directed to another directory by `-o` option\nor can be configured in the config file.\nYou can control the verbosity in the config file as well.\n\n### Output Visualization\n\n`scripts/plot_stats.py` can visualize some of the output (requires `matplotlib`):\n\n```bash\n# generate histograms from overall output\npython3 scripts/plot_stats dramsim3.json\n\n# or\n# generate time series for a variety stats from epoch outputs\npython3 scripts/plot_stats dramsim3epoch.json\n```\n\nCurrently stats from all channels are squashed together for cleaner plotting.\n\n### Integration with other simulators\n\n**Gem5** integration: works with a forked Gem5 version, see https://github.com/umd-memsys/gem5 at `dramsim3` branch for reference.\n\n**SST** integration: see http://git.ece.umd.edu/shangli/sst-elements/tree/dramsim3 for reference. We will try to merge to official SST repo.\n\n**ZSim** integration: see http://git.ece.umd.edu/shangli/zsim/tree/master for reference.\n\n## Simulator Design\n\n### Code Structure\n\n```\n├── configs                 # Configs of various protocols that describe timing constraints and power consumption.\n├── ext                     # \n├── scripts                 # Tools and utilities\n├── src                     # DRAMsim3 source files\n├── tests                   # Tests of each model, includes a short example trace\n├── CMakeLists.txt\n├── Makefile\n├── LICENSE\n└── README.md\n\n├── src  \n    bankstate.cc: Records and manages DRAM bank timings and states which is modeled as a state machine.\n    channelstate.cc: Records and manages channel timings and states.\n    command_queue.cc: Maintains per-bank or per-rank FIFO queueing structures, determine which commands in the queues can be issued in this cycle.\n    configuration.cc: Initiates, manages system and DRAM parameters, including protocol, DRAM timings, address mapping policy and power parameters.\n    controller.cc: Maintains the per-channel controller, which manages a queue of pending memory transactions and issues corresponding DRAM commands, \n                   follows FR-FCFS policy.\n    cpu.cc: Implements 3 types of simple CPU: \n            1. Random, can handle random CPU requests at full speed, the entire parallelism of DRAM protocol can be exploited without limits from address mapping and scheduling pocilies. \n            2. Stream, provides a streaming prototype that is able to provide enough buffer hits.\n            3. Trace-based, consumes traces of workloads, feed the fetched transactions into the memory system.\n    dram_system.cc:  Initiates JEDEC or ideal DRAM system, registers the supplied callback function to let the front end driver know that the request is finished. \n    hmc.cc: Implements HMC system and interface, HMC requests are translates to DRAM requests here and a crossbar interconnect between the high-speed links and the memory controllers is modeled.\n    main.cc: Handles the main program loop that reads in simulation arguments, DRAM configurations and tick cycle forward.\n    memory_system.cc: A wrapper of dram_system and hmc.\n    refresh.cc: Raises refresh request based on per-rank refresh or per-bank refresh.\n    timing.cc: Initiate timing constraints.\n```\n\n## Experiments\n\n### Verilog Validation\n\nFirst we generate a DRAM command trace.\nThere is a `CMD_TRACE` macro and by default it's disabled.\nUse `cmake .. -DCMD_TRACE=1` to enable the command trace output build and then\nwhenever a simulation is performed the command trace file will be generated.\n\nNext, `scripts/validation.py` helps generate a Verilog workbench for Micron's Verilog model\nfrom the command trace file.\nCurrently DDR3, DDR4, and LPDDR configs are supported by this script.\n\nRun\n\n```bash\n./script/validataion.py DDR4.ini cmd.trace\n```\n\nTo generage Verilog workbench.\nOur workbench format is compatible with ModelSim Verilog simulator,\nother Verilog simulators may require a slightly different format.\n\n\n## Related Work\n\n[1] Li, S., Yang, Z., Reddy D., Srivastava, A. and Jacob, B., (2020) DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator, IEEE Computer Architecture Letters.\n\n[2] Jagasivamani, M., Walden, C., Singh, D., Kang, L., Li, S., Asnaashari, M., ... \u0026 Yeung, D. (2019). Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die. IEEE Micro, 39(6), 64-72.\n\n[3] Li, S., Reddy, D., \u0026 Jacob, B. (2018, October). A performance \u0026 power comparison of modern high-speed DRAM architectures. In Proceedings of the International Symposium on Memory Systems (pp. 341-353).\n\n[4] Li, S., Verdejo, R. S., Radojković, P., \u0026 Jacob, B. (2019, September). Rethinking cycle accurate DRAM simulation. In Proceedings of the International Symposium on Memory Systems (pp. 184-191).\n\n[5] Li, S., \u0026 Jacob, B. (2019, September). Statistical DRAM modeling. In Proceedings of the International Symposium on Memory Systems (pp. 521-530).\n\n[6] Li, S. (2019). Scalable and Accurate Memory System Simulation (Doctoral dissertation).\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fumd-memsys%2FDRAMsim3","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fumd-memsys%2FDRAMsim3","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fumd-memsys%2FDRAMsim3/lists"}