{"id":23450717,"url":"https://github.com/undacmic/stm32g0x1xx","last_synced_at":"2026-02-18T14:36:12.247Z","repository":{"id":269302906,"uuid":"907003063","full_name":"undacmic/STM32G0x1xx","owner":"undacmic","description":"An easy to read template project written in C and ARMv6 Assembly for STM32G0x1xx microcontrollers that includes a linker script, startup code and SYSCLK initialization","archived":false,"fork":false,"pushed_at":"2024-12-28T19:48:47.000Z","size":10,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-02-15T19:48:41.878Z","etag":null,"topics":["arm","armv6-m","assembly","c","cortex-m","cortex-m0plus","embedded","embedded-systems","linker-script","microcontroller","nucleo-board","nucleo-g0b1re","startup-script","stm-32","stm32g0b1"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/undacmic.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-12-22T14:44:18.000Z","updated_at":"2024-12-28T19:48:50.000Z","dependencies_parsed_at":"2024-12-22T15:35:58.641Z","dependency_job_id":"fa953086-78c6-412b-87c7-2438a8f2452b","html_url":"https://github.com/undacmic/STM32G0x1xx","commit_stats":null,"previous_names":["undacmic/stm32g0x1xx"],"tags_count":0,"template":true,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/undacmic%2FSTM32G0x1xx","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/undacmic%2FSTM32G0x1xx/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/undacmic%2FSTM32G0x1xx/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/undacmic%2FSTM32G0x1xx/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/undacmic","download_url":"https://codeload.github.com/undacmic/STM32G0x1xx/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248198865,"owners_count":21063626,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["arm","armv6-m","assembly","c","cortex-m","cortex-m0plus","embedded","embedded-systems","linker-script","microcontroller","nucleo-board","nucleo-g0b1re","startup-script","stm-32","stm32g0b1"],"created_at":"2024-12-24T00:14:28.524Z","updated_at":"2026-02-18T14:36:07.205Z","avatar_url":"https://github.com/undacmic.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"\n\n### Downloading dependecies\n\n  - [STM32 Programming Toolset](https://github.com/stlink-org/stlink) + dependencies\n    ```sh\n    sudo apt-get install git make cmake libusb-1.0-0-dev\n    sudo apt-get install gcc build-essential\n\n    wget https://github.com/stlink-org/stlink/releases/download/v1.8.0/stlink_1.8.0-1_amd64.deb -q --show-progress\n    sudo dpkg -i stlink_1.8.0-1_amd64.deb\n    ```\n    Connect the board to an USB port and to test its connectivity you can execute the followind command:\n    \n    ```sh\n    lsusb | grep STM \n    Expected output: STMicroelectronics ST-LINK/V2.1\n    ```\n\n    The **COM LED** should also be **green**.\n    A problem with USB enumeration is indicated by a blinking red **COM LED**.\n\n    To see more specific information about the board you can execute the following command:\n    \u003cpre\u003e\n    st-info --probe\n\n    Found 1 stlink programmers\n        version:    V2J37S27\n        serial:     066BFF373146363143223537\n        \u003cspan style=\"background-color: rgba(245, 236, 39, 0.44)\"\u003eflash:      524288 (pagesize: 2048) \u003cb\u003e(512KB)\u003c/b\u003e\u003c/span\u003e\n        \u003cspan style=\"background-color: rgba(245, 236, 39, 0.44)\"\u003esram:       147456 \u003cb\u003e(144KB)\u003c/b\u003e\u003c/span\u003e\n        chipid:     0x467\n        dev-type:   STM32G0Bx_G0Cx\n    \u003c/pre\u003e\n\n## Startup Script\n\n### ARM Cortex-M0+ Reset Behavior\n\nThe Cortex-M0+ has the following reset behavior according to this well documented presentation [here](https://www.google.com/url?sa=t\u0026source=web\u0026rct=j\u0026opi=89978449\u0026url=https://community.arm.com/support-forums/f/soc-design-and-simulation-forum/54006/understanding-reset-sequence-cortex-m0\u0026ved=2ahUKEwjPjMOM3riKAxUfiv0HHXUTGkEQFnoECBcQAQ\u0026usg=AOvVaw0FCZVU6DNUNLWvWUzluuz3):\n  - Reads the **Initial SP**, also called the **MSP (Main Stack Pointer)** \n  - Reads the **reset vector**\n  - Branches to the starting of the program execution address (**reset handler**)\n  - Subsequently executes program instructions (TBD in the `Reset_Handler` function)\n\n### \n\n### `Reset_Handler`\n  A strong reference point was [this forum post](https://allthingsembedded.com/post/2019-01-03-arm-cortex-m-startup-code-for-c-and-c/) and also [this implementation](https://github.com/elzoughby/STM32H7xx-Startup/tree/master) for the **STM32H7xx** series.\n\n  1. Define the interrupt vector table for the NVIC according to the Cortex-M0+ Manual and STM32G0x1xx series reference Manual.\n\n  ```c\n  void (* g_pfnVectors[])(void) __attribute__((section (\".isr_vector\"))) = {...}\n  ```\n  2. Move the **MSP** to the **SP (Stack Pointer**) using inline assembly and `LDR` instruction _(see page 141 from ARMv6-m Architecture Manual)_. It uses the `_estack` symbol defined in the linker script.\n\n  ```c\n  __asm (\n        \"LDR R0, =_estack       \\n\\t\"\n        \"MOV SP, R0             \\n\\t\"\n    );\n  ```\n  3. Initialize the `.data` section. In order to use symbols from the ``.data`` section, the startup code needs to copy the data from ``LMA (Flash)`` to ``VMA (SRAM)`` to make sure that all C code can access the initialized data. It uses the `_data_start`, `data_end` symbols for the virtual adresses and `_sidata` symbol for the start address of the LMA of the `.data` section.\n\n  ```c\n  uint32_t *dataSrc = \u0026_sidata, *dataDest = \u0026_data_start;\n    while (dataDest \u003c \u0026_data_end) {\n        *dataDest++ = *dataSrc++;\n    }\n  ```\n  4. Initialize the `.bss` section to zero using inline assembly. It uses the `_bss_start` and `_bss_end` symbols defined in the linker script.\n\n  ```c\n    __asm (\n        \"LDR R0, =_bss_start      \\n\\t\"\n        \"LDR R1, =_bss_end        \\n\\t\"\n        \"MOV R2, #0               \\n\\t\"\n        \"loop_zero:               \\n\\t\"\n        \"   CMP \tR0, R1          \\n\\t\"\n        \"   BGE \tend_loop        \\n\\t\"\n        \"   STR\tR2, [R0]        \\n\\t\"\n        \"   ADD   R0, R0, #4      \\n\\t\"\n        \"   B \tloop_zero       \\n\\t\"\n        \"end_loop:                \\n\\t\"\n    );\n  ```\n### `System_Init`\nThe purpose of this function is to configure the `PLL Block` of the `Clock tree` with a frequency of **64 MHz** and to select `PLLRCLK` as the `SYSCLK` source.\n\nThe formula by which the output f\u003csub\u003ePLLR\u003c/sub\u003e is calculated is the following:\n\u003cpre\u003e\nf\u003csub\u003ePLLR\u003c/sub\u003e = ((f\u003csub\u003ePLLIN\u003c/sub\u003e / M) * N) / R,\nwhere:\n  - f\u003csub\u003ePLLIN\u003c/sub\u003e is the frequency of HSI16 clock source of 16 MHz\n  - M, N and R are configurable parameters using PLLCFGR register\n\u003c/pre\u003e\n\n\n### Documentation\n  - [STM32G0x1xx Reference Manual](https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)\n    * Memory Organization (Chapter 2.2.2 Memory map and register boundary addresses - **pg. 62**)\n    * System Clock Selection (Chapter 5. Reset and clock control (RCC) - **pg. 155**)\n  - [STM32 Cortex-M0/M0+ Programming Manual](https://www.st.com/resource/en/programming_manual/pm0223-stm32-cortexm0-mcus-programming-manual-stmicroelectronics.pdf)\n  - [ARMv6-M Architecture Reference Manual](https://www.google.com/url?sa=t\u0026source=web\u0026rct=j\u0026opi=89978449\u0026url=https://users.ece.utexas.edu/~valvano/mspm0/Arm_Architecture_v6m_Reference_Manual.pdf\u0026ved=2ahUKEwjn54aZnLmKAxX4nf0HHYpSDTkQFnoECBIQAQ\u0026usg=AOvVaw1wJfJ_0J4djK_M9sc94aE1)\n\n\n\n## Linker Script\n\n\n\n| **KEYWORD** | **DESCRIPTION**                                                                                                                                                                       |\n|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n| `SECTIONS`  | Defines the mapping between the sections of the input object files to the sections of the linker's output file, by specifying the memory layout of each output section.                |\n| `KEEP`      | Tells the linker to not remove the section wrapped by this command. Important when working with ARM microprocessors because the interrupt vector table must be in a predefined memory location and is not referenced directly by code. |\n| `LMA`       | Load Memory Address.                                                                                                                                                                  |\n| `VMA`       | Virtual Memory Address.                                                                                                                                                               |\n| `.`         | Location Counter.                                                                                                                                                                     |\n| `ALIGN`     | Introduces the required amount of padding to align the location counter.                                                                                                              |\n\n\n## Usage\n\nTo be able to run the rules inside the provided `Makefile` you are required to also install the [ARM GNU Toolchain](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):\n\n```sh\n  sudo apt-get install gcc-arm-none-eabi\n```\n\n1. Create `.hex` file using the Makefile rule:\n```sh\nmake all\n```\n2. Flash the device\n```sh\nst-flash --format ihex write program.hex\n\n2024-12-22T16:36:26 INFO common.c: STM32G0Bx_G0Cx: 144 KiB SRAM, 512 KiB flash in at least 2 KiB pages.\n2024-12-22T16:36:26 WARN common_flash.c: Flash base use default L0 address\n2024-12-22T16:36:26 INFO common_flash.c: Attempting to write 508 (0x1fc) bytes to stm32 address: 134217728 (0x8000000)\n-\u003e Flash page at 0x8000000 erased (size: 0x800)\n2024-12-22T16:36:26 INFO flash_loader.c: Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n\n2024-12-22T16:36:26 INFO common_flash.c: Starting verification of write complete\n2024-12-22T16:36:26 INFO common_flash.c: Flash written and verified! jolly good!\n2024-12-22T16:36:26 INFO common.c: Go to Thumb mode\n```\n\n(OPTIONAL) 3. Start a `gdb` connection using `st-util` and connect locally using `gdb-multiarch`\n\n```sh\nsudo apt-get install gdb-multiarch\n\n# Inside the first terminal window\nst-util\n\n# Inside the second terminal window\ngdb-multiarch\n\n(gdb) file program.hex\n(gdb) target remote localhost:4242\n(gdb) ...\n```","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fundacmic%2Fstm32g0x1xx","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fundacmic%2Fstm32g0x1xx","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fundacmic%2Fstm32g0x1xx/lists"}