{"id":21297607,"url":"https://github.com/uttamsdev/risc-cpu-implementation","last_synced_at":"2025-07-12T18:32:44.347Z","repository":{"id":242129961,"uuid":"808320087","full_name":"uttamsdev/RISC-CPU-Implementation","owner":"uttamsdev","description":"14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.","archived":false,"fork":false,"pushed_at":"2024-05-30T20:30:28.000Z","size":362,"stargazers_count":4,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-06-19T21:37:48.788Z","etag":null,"topics":["14bit-cpu","risc-cpu-implementation"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/uttamsdev.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-05-30T20:28:53.000Z","updated_at":"2024-07-15T20:49:55.000Z","dependencies_parsed_at":"2024-05-31T20:39:22.681Z","dependency_job_id":null,"html_url":"https://github.com/uttamsdev/RISC-CPU-Implementation","commit_stats":null,"previous_names":["uttamsdev/risc-cpu-implementation"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/uttamsdev/RISC-CPU-Implementation","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/uttamsdev%2FRISC-CPU-Implementation","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/uttamsdev%2FRISC-CPU-Implementation/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/uttamsdev%2FRISC-CPU-Implementation/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/uttamsdev%2FRISC-CPU-Implementation/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/uttamsdev","download_url":"https://codeload.github.com/uttamsdev/RISC-CPU-Implementation/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/uttamsdev%2FRISC-CPU-Implementation/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":265032986,"owners_count":23700915,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["14bit-cpu","risc-cpu-implementation"],"created_at":"2024-11-21T14:39:18.156Z","updated_at":"2025-07-12T18:32:44.327Z","avatar_url":"https://github.com/uttamsdev.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 14-bit-RISC-CPU-Implementation\n14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository. Datapath, Register Circut,Register File\n1 bit ALU, 14 bit ALU, Final ALU, Control Signals and Control Unit\n\n# Designed by Uttam Kumar Saha\n\n# Datapath Design:\n![](/Images/datapath.png)\n\n\n# Register Circuit:\n![](Images/regCircuit.png)\n\n\n# Register File:\n![](Images/RegFile.png)\n\n# ALU Circuit:\n![](Images/ALU%20circuit.png)\n\n\n# 1-bit ALU:\n![](Images/1-bit-ALU.png)\n\n\n\n# 14 bit ALU:\n![](Images/14%20bit%20ALU.png)\n\n\n# Final ALU:\n![](Images/final%20ALU.png)\n\n# Shifter Circuit:\n![](Images/shifterCircuit.png)\n\n# Control Signals Circuit 1:\n![](Images/Control%20Signal%20Circuit1.png)\n\n# Control Signal Circuit 2:\n![](Images/Control%20Signal%20Circuit2.png)\n\n# Control Unit 1:\n![](Images/control%20unit%201.png)\n\n# Control Unit 2:\n![](Images/control%20unit%202.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Futtamsdev%2Frisc-cpu-implementation","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Futtamsdev%2Frisc-cpu-implementation","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Futtamsdev%2Frisc-cpu-implementation/lists"}