{"id":21294697,"url":"https://github.com/vaquierm/mips-processor-simulation","last_synced_at":"2025-03-15T17:12:55.806Z","repository":{"id":67006524,"uuid":"172253156","full_name":"vaquierm/MIPS-Processor-Simulation","owner":"vaquierm","description":"💾 Improvement to a MIPS processor simulation written in Java. Benchmarks used to track improvements of specific changes","archived":false,"fork":false,"pushed_at":"2019-04-11T16:31:41.000Z","size":8171,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-03-14T22:32:04.376Z","etag":null,"topics":["mips-architecture","mips-assembly","mips-simulator","pipeline-processor"],"latest_commit_sha":null,"homepage":"","language":"Java","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/vaquierm.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-02-23T19:11:03.000Z","updated_at":"2020-03-06T22:34:36.000Z","dependencies_parsed_at":"2023-05-20T08:45:35.908Z","dependency_job_id":null,"html_url":"https://github.com/vaquierm/MIPS-Processor-Simulation","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vaquierm%2FMIPS-Processor-Simulation","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vaquierm%2FMIPS-Processor-Simulation/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vaquierm%2FMIPS-Processor-Simulation/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/vaquierm%2FMIPS-Processor-Simulation/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/vaquierm","download_url":"https://codeload.github.com/vaquierm/MIPS-Processor-Simulation/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243762267,"owners_count":20343979,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["mips-architecture","mips-assembly","mips-simulator","pipeline-processor"],"created_at":"2024-11-21T14:00:20.168Z","updated_at":"2025-03-15T17:12:55.761Z","avatar_url":"https://github.com/vaquierm.png","language":"Java","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MIPS-Processor-Simulation\n\nThe proposed project is to explore the effects of different cache structures on the read, write and overall average memory access time as well as the total number of stalls in the pipeline due to structural hazards caused by the memory module.\nThe simulator that was modified is [EduMIPS64](https://www.edumips.org/)\n\n# Repository Structure\nThe *Benchmarks* folder is as was provided to us, while the remainder is the actual edumips64 implementation. \n\nAll configuration JSON files used for testing can be found in *cache_config/configs/* and the resulting JSON files corresponding to these tests can be found in  *cache_config/results/*. The majority of the cache implementation code is located in *edumips64/cache/*, and the ui adjustments were done in the main class like the other buttons.\n\nThe *python/* folder contains all the jupyter notebooks used for calculating the results and generating the graphs of the cache behaviour.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"imgs/tree2.png\" /\u003e\n\u003c/p\u003e\n\n# Cache Abstraction Class Diagram\n\nBelow is the class diagram of the new module that was developed to simulate a cache.  TheCacheMan-ageris the most important class were most of the calls from the existing system go through.  thesetupmethod can ingest the file path of the JSON configuration file which will create a set ofDirectMapped-CacheLayerandSetAssociativeCacheLayerobjects that represents the configuration.   Later on,  whenmemory accesses are made, thecalculateLatencymethod is called to calculate how many cycles a parti-cluar access at a specific address takes with the current cache state.The only two concrete classes for Cache layers are theDirectMappedCacheLayerand theSetAssociative-CacheLayerwhich have different internal mechanics for placing and replacing blocks. However both ofthese classes implement theICacheLayerinterface which concists of all methods needed by theCache-Managerto calculate the memory latency for the whole cache structure. The general fields shared amongall types of caches are stored in theCacheLayerabstract class.Lastly, theCacheBlockis the abstraction for a block in the cache.  It is contained by theCacheLayerclass  so  that  it  can  keep  track  of  all  the  block  currently  in  that  layer  and  the  validity  of  each  block.SetAssociativeCacheLayeruses thePriorityCacheBlockto keep track of what to evict next with respectto its eviction policy.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"imgs/class_diagram_cache.png\" /\u003e\n\u003c/p\u003e\n\n# Results found\n\nFor each test, a particular parameter of the cache was changed in an isolated way. The results can be seen in the */pyhon* folder of the improved repository. The metric that is observed is the average memory access time measured in clock cycles.\n\n- [Comparing the associativity](https://github.com/vaquierm/MIPS-Processor-Simulation/blob/master/edumips64-0.5.3-Improved/python/Associativity.ipynb) (From direct mapping to Fully associative)\n- [Comparing the cache size to block size ratio](https://github.com/vaquierm/MIPS-Processor-Simulation/blob/master/edumips64-0.5.3-Improved/python/Cache_Block_to_Size_Ratio_Comparaison.ipynb)\n- [Comparing the number of levels in the cache](https://github.com/vaquierm/MIPS-Processor-Simulation/blob/master/edumips64-0.5.3-Improved/python/Number_of_levels_comparaison.ipynb)\n- [Comparing the replacement policies](https://github.com/vaquierm/MIPS-Processor-Simulation/blob/master/edumips64-0.5.3-Improved/python/Replacement_Policies.ipynb) (For Fully and set associative)\n- [Comparing the write strategies](https://github.com/vaquierm/MIPS-Processor-Simulation/blob/master/edumips64-0.5.3-Improved/python/Write_Strategies.ipynb) (*write through* and *write back*)\n\n# How to load a new cache configuration and export statistics\n\n**1. Load the configuration file**\n\n\u003cimg src=\"imgs/CacheConfigBar.png\" width=\"350\"/\u003e\n\u003cimg src=\"imgs/ChooseFileDialog.png\" width=\"350\"/\u003e\n\u003cimg src=\"imgs/ConfirmLoad.png\" width=\"650\"/\u003e\n\n**2. Load the simulation file**\n\n\u003cimg src=\"imgs/open_file.png\" width=\"200\"/\u003e\n\n**3. Run the simulation**\n\n*F4* for running te whole progream\n*F7* for single step\n\n**4. Export statistics**\n\n\u003cimg src=\"imgs/export.png\" width=\"350\"/\u003e\n\u003cimg src=\"imgs/ExportDialog.png\" width=\"350\"/\u003e\n\n**5. Either: Clear the current cache config or load a new config**\n\n\u003cimg src=\"imgs/ClearCache.png\" width=\"350\"/\u003e\n\u003cimg src=\"imgs/ClearCacheConfirm.png\" width=\"250\"/\u003e\n\n# Format of configuration file\n\nThere are certain parameters that are required to load a cache configuration, such as *mmat* and *caches*. *Caches* can be left as an empty list if there are no caches in the specified configuration.  However, if there is a cache object then the following parameters that will need to be provided are *size*, *blockSize*, *accessTime*, *mappingScheme* and *writeStrategy*. *Size* and *blockSize* have to be powers of 2, must have a postfix of *B*, *KB* or *MB* to indicate bytes, kilobytes or megabytes and must have a blockSize smaller or equal to size. *AccessTime* should preferably for a cache be smaller than the main memory access time.\nFor *mappingScheme* the options are:\n- DIRECT\n- N_WAY_SET_ASSOCIATIVE_LRU (where N is an integer multiple of 2)\n- N_WAY_SET_ASSOCIATIVE_FIFO\n- N_WAY_SET_ASSOCIATIVE_RANDOM\n- FULLY_ASSOCIATIVE_LRU\n- FULLY_ASSOCIATIVE_RANDOM\n- FULLY_ASSOCIATIVE_FIFO\n\nLastly for *writeStrategy*, the available options are:\n- WRITEBACK (which uses a write back write allocate strategy)\n- WRITETHROUGH (which uses a write through no write allocate strategy)\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"imgs/cache_config_example.PNG\" width=\"350\"/\u003e\n\u003c/p\u003e\n\n# Format of the result files\n\nThe result file contains all the information that was already in the configuration file such that the user can see what the configuration that was used for the run. The name of the benchmark file that the test ran on is also included as *benchmark\\_name*. Additionally, the average memory access time overall, for read accesses, and for write accesses (*amat*, *amat_read*, *amat_write*} respectively). Finally, The hit rate of each cache layer is present so that the user can identify were the bottleneck is when the average memory access time is higher than expected.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"imgs/cache_result_file_example.PNG\" width=\"450\"/\u003e\n\u003c/p\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvaquierm%2Fmips-processor-simulation","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fvaquierm%2Fmips-processor-simulation","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fvaquierm%2Fmips-processor-simulation/lists"}